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toshiba toshiba corporation 1 tlcs-900 series TMP96C141AF the information contained here is subject to change without notice. the information contained herein is presented only as guide for the applications of our products. no responsibility is assumed by toshiba for any infringements of patents or other rights of the third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of toshiba or others. these toshiba products are intended for usage in general electronic equipments (of?e equipment, communication equipment, measuring equipment, domestic electri?ation, etc.) please make sure that you consult with us before you use these toshiba products in equip- ments which require high quality and/or reliability, and in equipments which could have major impact to the welfare of human life (atomic energy control, spaceship, traf? signal, combustion control, all types of safety devices, etc.). toshiba cannot accept liability to any damage which may occur in case these toshiba products were used in the mentioned equipments without prior consultation with toshiba. cmos 16-bit microcontroller TMP96C141AF 1. outline and device characteristics the TMP96C141AF is high-speed advanced 16-bit microcon- troller developed for controlling medium to large-scale equip- ment. the TMP96C141AF is housed in an 80-pin ?t package. device characteristics are as follows: (1) original 16-bit cpu tlcs-90 instruction mnemonic upward compatible. 16m-byte linear address space general-purpose registers and register bank system 16-bit multiplication/division and bit transfer/arithmetic instructions high-speed micro dma - 4 channels (1.6 m s/2 bytes @ 20mhz) (2) minimum instruction execution time - 200ns @ 20mhz (3) internal ram: 1k byte internal rom: none (4) external memory expansion can be expanded up to 16m bytes (for both programs and data). can mix 8- and 16-bit external data buses. ? dynamic data bus sizing (5) 8-bit timers: 2 channels (6) 8-bit pwm timers: 2 channels (7) 16-bit timers: 2 channels (8) pattern generators: 4 bits, 2 channels (9) serial interface: 2 channels (10) 10-bit a/d converter: 4 channels (11) watchdog timer (12) chip select/wait controller: 3 blocks (13) interrupt functions 3 cpu interrupts ? ? swi instruction, privileged violation, and illegal instruction 14 internal interrupts 6 external interrupts (14) i/o ports (15) standby function : 3 halt modes (run, idle, stop) 7-level priority can be set.
2 toshiba corporation TMP96C141AF figure 1. TMP96C141AF block diagram
toshiba corporation 3 TMP96C141AF 2. pin assignment and functions the assignment of input/output pins for TMP96C141AF, their name and outline functions are described below. figure 2.1 pin assignment (80-pin qfp) 2.1 pin assignment figure 2.1 shows pin assignment of TMP96C141AF.
4 toshiba corporation TMP96C141AF 2.2 pin names and functions the names of input/output pins and their functions are described below. note: with the external dma controller, this devices built-in memory or built-in i/o cannot be accessed using the busrq and busak pins. table 2.2. pin names and functions pin name number of pins i/o functions p00 ~ p07 ad0 ~ ad7 8 i/o tri-state port 0: i/o port that allows i/o to be selected on a bit basis address / data (lower): 0 - 7 for address / data bus p10 ~ p17 ad8 ~ ad15 a8 ~ a15 8 i/o tri-state output port 1: i/o port that allows i/o to be selected on a bit basis address data (upper): 8 - 15 for address / data bus address: 8 to 15 for address bus p20 ~ p27 a0 ~ a7 a16 ~ a23 8 i/o output output port 2: i/o port that allows selection of i/o on a bit basis (with pull-down resistor) address: 0 - 7 for address bus address: 16 - 23 for address bus p30 rd 1 output output port 30: output port read: strobe signal for reading external memory p31 wr 1 output output port 31: output port write: strobe signal for writing data on pins ad0 -7 p32 hwr 1 i/o output port 32: i/o port (with pull-up resistor) high write: strobe signal for writing data on pins ad8 - 15 p33 w ait 1 i/o input port 33: i/o port (with pull-up resistor) wait: pin used to request cpu bus wait p34 busrq 1 i/o input port 34: i/o port (with pull-up resistor) bus request: signal used to request high impedance for ad0 - 15, a0 - 23, rd , wr , hwr , r/w , ras , cs0 , cs1 , and cs2 pins. (for external dmac) p35 busak 1 i/o output port 35: i/o (with pull-up resistor) bus acknowledge: signal indicating that ad0 - 15, a0 - 23, rd , wr , hwr , r/w , ras , cs0 , cs1 , and cs2 pins are at high impedance after receiving busrq. (for external dmac) p36 r/w 1 i/o output port 36: i/o port (with pull-up resistor) read/write: 1 represents read or dummy cycle; 0, write cycle. p37 ras 1 i/o output port 37: i/o port (with pull-up resistor) row address strobe: outputs ras strobe for dram. p40 cs0 cas0 1 i/o output output port 40: i/o port (with pull-up resistor) chip select 0: outputs 0 when address is within speci?d address area. column address strobe 0: outputs cas strobe for dram when address is within speci?d address area.
toshiba corporation 5 TMP96C141AF pin name number of pins i/o functions p41 cs1 cas1 1 i/o output output port 41: i/o port (with pull-up resistor) chip select 1: outputs 0 if address is within speci?d address area. column address strobe 1: outputs cas strobe for dram if address is within speci?d address area. p42 cs2 cas2 1 i/o output output port 42: i/o port (with pull-up resistor) chip select 2: outputs 0 if address is within speci?d address area. column address strobe 2: outputs cas strobe for dram if address is within speci?d address area. p50 ~ p53 an0 ~ an3 4 input input port 5: input port analog input: input to a/d converter vref 1 input pin for reference voltage input to a/d converter agnd 1 input ground pin for a/d converter p60 ~ p63 pg00 ~ pg03 4 i/o output ports 60 - 63: i/o ports that allow selection of i/o on a bit basis (with pull-up resistor) pattern generator ports: 00 - 03 p64 ~ p67 pg10 ~ pg13 4 i/o output ports 64 - 67: i/o ports that allow selection of i/o on a bit basis (with pull-up resistor) pattern generator ports: 10 - 13 p70 t10 1 i/o input port 70: i/o port (with pull-up resistor) timer input 0: timer 0 input p71 t01 1 i/o output port 71: i/o port (with pull-up resistor) timer output 1: timer 0 or 1 output p72 t02 1 i/o output port 72: i/o port (with pull-up resistor) pwm output 2: 8-bit pwm timer 2 output p73 t03 1 i/o output port 73: i/o port (with pull-up resistor) pwm output 3: 8-bit pwm timer 3 output p80 ti4 int4 1 i/o input input port 80: i/o port (with pull-up resistor) timer input 4: timer 4 count/capture trigger signal input interrupt request pin 4: interrupt request pin with programmable rising/falling edge p81 ti5 int5 1 i/o input input port 81: i/o port (with pull-up resistor) timer input 5: timer 4 count/capture trigger signal input interrupt request pin 5: interrupt request pin with rising edge p82 to4 1 i/o output port 82: i/o port (with pull-up resistor) timer output 4: timer 4 output pin p83 to5 1 i/o output port 83: i/o port (with pull-up resistor) timer output 5: timer 4 output pin
6 toshiba corporation TMP96C141AF note: pull-up/pull-down resistor can be released from the pin by software. pin name number of pins i/o functions p84 ti6 int6 1 i/o input input port 84: i/o port (with pull-up resistor) timer input 6: timer 5 count/capture trigger signal input interrupt request pin 6: interrupt request pin with programmable rising/falling edge p85 ti7 int7 1 i/o input input port 85: i/o port (with pull-up resistor) timer input 7: timer 5 count/capture trigger signal input interrupt request pin 7: interrupt request pin with rising edge p86 to6 1 i/o output port 86: i/o port (with pull-up resistor) timer output 6: timer 5 output pin p87 int0 1 i/o input port 87: i/o port (with pull-up resistor) interrupt request pin 0: interrupt request pin with programmable level/rising edge p90 txd0 1 i/o output port 90: i/o port (with pull-up resistor) serial send data 0 p91 rxd0 1 i/o input port 91: i/o port (with pull-up resistor) serial receive data 0 p92 cts0 1 i/o input port 92: i/o port (with pull-up resistor) serial data send enable 0 (clear to send) p93 txd1 1 i/o output port 93: i/o port (with pull-up resistor) serial send data 1 p94 rxd1 1 i/o input port 94: i/o port (with pull-up resistor) serial receive data 1 p95 sclk1 1 i/o i/o port 95: i/o port (with pull-up resistor) serial clock i/o 1 wdtout 1 output watchdog timer output pin nmi 1 input non-maskable interrupt request pin: interrupt request pin with falling edge. can also be operated at rising edge by program. clk 1 output clock output: outputs x1 ? 4 clock. pulled-up during reset. ea 1 input external access: 0 should be inputted with TMP96C141AF 1, with tmp96cm40f/tmp96pm40f. ale 1 output address latch enable reset 1 input reset: initializes lsi. (with pull-up resistor) x1/x2 2 i/o oscillator connecting pin vcc 2 power supply pin (+ 5v) vss 3 gnd pin (0v)
toshiba corporation 7 TMP96C141AF 3. operation this section describes in blocks the functions and basic oper- ations of the TMP96C141AF device. check the chapter guidelines and restrictions for proper care of the device. 3.1 cpu the TMP96C141AF device has a built-in high-performance 16-bit cpu. (for cpu operation, see tlcs-900 cpu in the book core manual architecture user manual.) this section describes cpu functions unique to TMP96C141AF that are not described in that manual. 3.1.1 reset to reset the TMP96C141AF, the reset input must be kept at 0 for at least 10 system clocks (10 states: 1 m s with a 20mhz system clock) within an operating voltage range and with a stable oscillation. when reset is accepted, the cpu sets as follows: program counter (pc) to 8000h. stack pointer (xsp) for system mode to 100h. sysm bit of status register (sr) to 1. (sets to system mode.) iff2 to 0 bits of status register to 111. (sets mask register to interrupt level 7.) max bit of status register to 0. (sets to minimum mode.) bits rfp2 to 0 of status register to 000. (sets register banks to 0.) when reset is released, instruction execution starts from address 8000h. cpu internal registers other than the above are not changed. when reset is accepted, processing for built-in i/os, ports, and other pins is as follows: initializes built-in i/o registers as per specifications. sets port pins (including pins also used as built-in i/os) to general-purpose input/output port mode (sets i/o ports to input ports). sets the wdtout pin to 0. (watchdog timer is set to enable after reset.) pulls up the clk pin to 1. sets the ale pin to 0.
8 toshiba corporation TMP96C141AF 3.2 memory map figure 3.2 is a memory map of the TMP96C141AF. figure 3.2 memory map
toshiba corporation 9 TMP96C141AF 3.3 interrupts the tlcs-900 interrupts are controlled by the cpu interrupt mask ?p-?p (iff2 to 0) and the built-in interrupt controller. the TMP96C141AF have altogether the following 23 interrupt sources: a ?ed individual interrupt vector number is assigned to each interrupt source; six levels of priority (variable) can also be assigned to each maskable interrupt. non-maskable inter- rupts have a ?ed priority of 7. when an interrupt is generated, the interrupt controller sends the value of the priority of the interrupt source to the cpu. when more than one interrupt is generated simulta- neously, the interrupt controller sends the value of the highest priority (7 for non-maskable interrupts is the highest) to the cpu. the cpu compares the value of the priority sent with the value in the cpu interrupt mask register (iff2 to 0). if the value is greater than that of the cpu interrupt mask register, the interrupt is accepted. the value in the cpu interrupt mask reg- ister (iff2 to 0) can be changed using the ei instruction (con- tents of the ei num/iff<2:0> = num). for example, programming ei 3 enables acceptance of maskable interrupts with a priority of 3 or greater, and non-maskable interrupts which are set in the interrupt controller. the di instruction interrupts from the cpu 3 (software interrupts, privileged violations, and illegal (unde?ed) instruction execution) interrupts from external pins (nmi, int0, and int4 to 7) 6 interrupts from built-in i/os 14 (iff<2:0> = 7) operates in the same way as the ei 7 instruc- tion. since the priority values for maskable interrupts are 0 to 6, the di instruction is used to disable maskable interrupts to be accepted. the ei instruction becomes effective immediately after execution. (with the tlcs-90, the ei instruction becomes effective after execution of the subsequent instruction.) in addition to the general-purpose interrupt processing mode described above, there is also a high-speed micro dma processing mode. high-speed micro dma is a mode used by the cpu to automatically transfer byte or word data. it enables the cpu to process interrupts such as data saves to built-in i/os at high speed. figure 3.3 (1) is a ?wchart showing overall interrupt processing.
10 toshiba corporation TMP96C141AF figure 3.3 (1) interrupt processing flowchart
toshiba corporation 11 TMP96C141AF 3.3.1 general-purpose interrupt processing when accepting an interrupt, the cpu operates as follows: (1) the cpu reads the interrupt vector from the interrupt controller. when more than one interrupt with the same level is generated simultaneously, the interrupt controller generates interrupt vectors in accordance with the default priority (which is ?ed as follows: the smaller the vector value, the higher the priority), then clears the inter- rupt request. (2) the cpu pushes the program counter and the status register to the system stack area (area indicated by the system mode stack pointer). (3) the cpu sets a value in the cpu interrupt mask register that is higher by 1 than the value of the accepted interrupt level. however, if the value is 7, 7 is set without an increment. (4) the cpu sets the ?g of the status register to 1 and enters the system mode. (5) the cpu jumps to address 8000h + interrupt vector, then starts the interrupt processing routine. in minimum mode, all the above processing is completed in (1.5 m s @ 20mhz). in maximum mode, it is com- pleted in 17 states. 15 states to return to the main routine after completion of the inter- rupt processing, the reti instruction is usually used. executing this instruction restores the contents of the program counter and the status registers. though acceptance of non-maskable interrupts cannot be disabled by program, acceptance of maskable interrupts can. a priority can be set for each source of maskable inter- rupts. the cpu accepts an interrupt request with a priority higher than the value in the cpu mask register . the cpu mask register is set to a value higher by 1 than the priority of the accepted interrupt. thus, if an inter- rupt with a level higher than the interrupt being processed is generated, the cpu accepts the interrupt with the higher level, causing interrupt processing to nest. the cpu does not accept an interrupt request of the same level as that of the interrupt being processed. resetting initializes the cpu mask registers to 7; therefore, maskable interrupts are disabled. the addresses 008000h to 0081ffh (512 bytes) of the tlcs-900 are assigned for interrupt processing entry area. bus width of stack area interrupt processing state number max mode min mode 8 bit 23 19 16 bit 17 15
12 toshiba corporation TMP96C141AF table 3.3 (1) TMP96C141AF interrupt table default priority type interrupt source vector value ? start address high-speed micro dma start vector 1 non- maskable reset , or sw10 instruction 0000h 8000h 2 intprev: privileged violation, or swi1 0010h 8010h 3 intundef: illegal instruction, or swi2 0020h 8020h 4 swi 3 instruction 0030h 8030h 5 swi 4 instruction 0040h 8040h 6 swi 5 instruction 0050h 8050h 7 swi 6 instruction 0060h 8060h 8 swi 7 instruction 0070h 8070h 9 nmi pin 0080h 8080h 08h 10 intwd: watchdog timer 0090h 8090h 09h 11 maskable into pin 00a0h 80a0h 0ah 12 int4 pin 00b0h 80b0h 0bh 13 int5 pin 00c0h 80c0h 0ch 14 int6 pin 00d0h 80d0h 0dh 15 int7 pin 00e0h 80e0h 0eh - (reserved) 00f0h 80f0h 0fh 16 intt0: 8-bit timer 0 0100h 8100h 10h 17 intt1: 8-bit timer 1 0110h 8110h 11h 18 intt2: 8-bit timer 2/pwm0 0120h 8120h 12h 19 intt3: 8-bit timer 3/pwm1 0130h 8130h 13h 20 inttr4: 16-bit timer 4 (treg4) 0140h 8140h 14h 21 inttr5: 16-bit timer 4 (treg5) 0150h 8150h 15h 22 inttr6: 16-bit timer 5 (treg6) 0160h 8160h 16h 23 inttr7: 16-bit timer 5 (treg7) 0170h 8170h 17h 24 intrx0: serial receive (channel.0) 0180h 8180h 18h 25 inttx0: serial send (channel.0) 0190h 8190h 19h 26 intrx1: serial receive (channel.1) 01a0h 81a0h 1ah 27 inttx1: serial send (channel.1) 01b0h 81b0h 1bh 28 intad: a / d conversion completion 0 1 c 0 h 81c0h 1ch (reserved) 01d0h 81d0h 1dh (reserved) 01e0h 81e0h 1eh (reserved) 01f0h 81f0h 1fh 3.3.2 high-speed micro dma in addition to the conventional interrupt processing, the tlcs- 900 also has a high-speed micro dma function. when an interrupt is accepted, in addition to an interrupt vector, the cpu receives data indicating whether processing is high-speed micro dma mode or general-purpose interrupt. if high-speed micro dma mode is requested, the cpu performs high-speed micro dma processing. the tlcs-900 can process at very high speed com- pared with the tlcs-90 micro dma because it has transfer parameters in dedicated registers in the cpu. since those dedicated registers are assigned as cpu control registers, they can only be accessed by the ldc (privileged) instruction.
toshiba corporation 13 TMP96C141AF (1) high-speed micro dma operation high-speed micro dma operation starts when the accepted interrupt vector value matches the micro dma start vector value set in the interrupt controller. the high-speed micro dma has four channels so that it can be set for up to four types of interrupt source. when a high-speed micro dma interrupt is accepted, data is automatically transferred from the transfer source address to the transfer destination address set in the control register, and the transfer counter is decremented. if the value in the counter after decrementing is other than 0, high-speed micro dma processing is completed. if the value in the counter after decrementing is 0, general-purpose interrupt processing is performed. in read-only mode, which is provided for dram refresh, the value in the counter is ignored and dummy read is repeated. the 32-bit control registers are used for setting transfer source/destination addresses. however, the tlcs-900 has only 24 address pins for output. a 16m-byte space is available for the high-speed micro dma. also in normal mode operation, the all address space (in other words, the space for system mode which is set by the cs/wait controller) can be accessed by high-speed micro dma processing. there are two data transfer modes: one-byte mode and one-word mode. incrementing, decrementing, and ?ing the transfer source/destination address after transfer can be done in both modes. therefore data can easily be transferred betweeni/o and memory and between i/os. for details of transfer modes, see the description of transfer mode registers. the transfer counter has 16 bits, so up to 65536 trans- fers (the maximum when the initial value of the transfer counter is 0000h) can be performed for one interrupt source by high- speed micro dma processing. a the data transferred by the m dma function, the transfer nter was decreased. when this counter is ??, the processor operates gen- eral interrupt processing. at this time if the same channel of interrupt is required next interrupt, the transfer counter starts from 65536. interrupt sources processed by high-speed micro dma processing are those with the high-speed micro dma start vectors listed in table 3.3 (1).
14 toshiba corporation TMP96C141AF the following timing chart is a high-speed m dma cycle of the transfer address increment mode (the other mode exe- cept the read-only mode is same as this) (condition: min mode, 16bit bus width for 16m byte, 0 wait) (2) register con?uration (cpu control register) these control registers cannot be set only ?cd cr, r?instruction.
toshiba corporation 15 TMP96C141AF (3) transfer mode register details this condition is 16-bit bus width and 0 wait of source/destination address space. note: n: corresponds to high-speed m dma channels 0 - 3. dmadn +/dmasn + : post-increment (increments register value after transfer.) dmadn -/dmasn - : post-decrement (decrement register value after transfer.) all address space (the space for system mode) can be accessed by high-speed m dma. do not use unde?ed codes for transfer mode control.
16 toshiba corporation TMP96C141AF when the hardware con?uration is as follows: dram mapping size: = 1mb dram data bus size: = 8 bits dram mapping address range: = 100000h to 1fffffh set the following registers ?st; refresh is performed automatically. register initial value setting ld xix, 100000h ldc dmas0,xix mapping start address ld a, 00001010b ldc dmam0, a read only mode (for dram refresh) timer setting set the timers so that interrupts are generated at intervals of 62.5 m s or less. a interrupt controller setting set the timer interrupt mask h other interrupt mask. write the above timer interrupt vector value in the high-speed m dma start vector register, dma0v. (operation description) the dram data bus is an 8-bit bus and the micro dma is in read-only mode (4 bytes), so refresh is per- formed four times per interrupt. when a 512 refresh/8ms dram is connected, dram refresh is performed suf?iently if the micro dma is started every 15.625 m s x 4 = 62.4 m s or less, since the timing is 15.625 m s/refresh. (overhead) each processing time by the micro dma is 1.8 m s (18 states) @ 20mhz with an 8-bit data bus. in the above example, the micro dma is started every 62.5 m s, 1.8 m s/62.5 m s = 0.029; thus, the overhead is 2.9%. 3.3.3 interrupt controller figure 3.3.3 (1) is a block diagram of the interrupt circuits. the left half of the diagram shows the interrupt controller; the right half includes the cpu interrupt request signal circuit and the halt release signal circuit. each interrupt channel (total of 20 channels) in the inter- rupt controller has an interrupt request ?p-?p, interrupt prior- ity setting register, and a register for storing the high-speed micro dma start vector. the interrupt request ?p-?p is used to latch interrupt requests from peripheral devices. the ?p-?p is cleared to 0 at reset, when the cpu reads the interrupt channel vector after the acceptance of interrupt, or when the cpu executes an instruction that clears the interrupt of that channel (writes 0 in the clear bit of the interrupt priority setting register). for example, to clear the int0 interrupt request, set the register after the as follows. inte0ad ? ---- 0 --- zero-clears the int0 flip-flop. the status of the interrupt request ?p-?p is detected by reading the clear bit. detects whether there is an interrupt request for an interrupt channel. the interrupt priority can be set by writing the priority in the interrupt priority setting register (e.g., inte0ad, inte45, etc.) provided for each interrupt source. interrupt levels to be set are from 1 to 6. writing 0 or 7 as the interrupt priority dis- ables the corresponding interrupt request. the priority of the non-maskable interrupt (nmi pin, watchdog timer, etc.) is ?ed to 7. if interrupt requests with the same interrupt level are gen- erated simultaneously, interrupts are accepted in accordance with the default priority (the smaller the vector value, the higher the priority). the interrupt controller sends the interrupt request with the highest priority among the simultaneous interrupts and its vector address to the cpu. the cpu compares the priority value set in the status register by the interrupt request signal with the priority value sent; if the latter is higher, the interrupt is accepted. then the cpu sets a value higher than the priority value by 1 in the cpu sr. interrupt requests where the priority value equals or is higher than the set value are accepted simultaneously during the previous interrupt routine. when interrupt processing is completed (after execution of the reti instruction), the cpu restores the priority value saved in the stack before the interrupt was generated to the cpu sr. the interrupt controller also has four registers used to store the high-speed micro other dma start vector. these are i/ o registers; unlike other dma registers (dmas, dmad, dmam, and dmac), they can be accessed in either normal or system mode. writing the start vector of the interrupt source for the micro dma processing (see table 3.3 (1)), enables the corre- sponding interrupt to be processed by micro dma processing. the values must be set in the micro dma parameter registers (e.g., dmas and dmad) prior to the micro dma processing. di instruction
toshiba corporation 17 TMP96C141AF figure 3.3.3 (1) block diagram of interrupt controller
18 toshiba corporation TMP96C141AF (1) interrupt priority setting register
toshiba corporation 19 TMP96C141AF (2) external interrupt control
20 toshiba corporation TMP96C141AF micro dma0 start vector 76543210 bit symbol dma0v8 dma0v7 dma0v6 dma0v5 dma0v4 read / write w after reset 00000 micro dma1 start vector 76543210 bit symbol dma1v8 dma1v7 dma1v6 dma1v5 dma1v4 read / write w after reset 00000 micro dma2 start vector 76543210 bit symbol dma2v8 dma2v7 dma2v6 dma2v5 dma2v4 read / write w after reset 00000 micro dma3 start vector 76543210 bit symbol dma3v8 dma3v7 dma3v6 dma3v5 dma3v4 read / write w after reset 00000 dma0v (007ch) dma1v (007dh) dma2v (007eh) dma3v (007fh) (read-modify-write is not possible.) (read-modify-write is not possible.) (read-modify-write is not possible.) (read-modify-write is not possible.) (3) high-speed micro dma start vector when the cpu reads the interrupt vector after accepting an inter- rupt, it simultaneously compares the interrupt vector with each channels micro dma start vector (bits 4 to 8 of the interrupt vec- tor). when both match, the interrupt is processed in micro dma mode for the channel whose value matched. if the interrupt vector matches more than one chan- nel, the channel with the lower channel number has a higher priority. (4) notes the instruction execution unit and the bus interface unit of this cpu operate independently of each other. therefore, if the instruc- tion used to clear an interrupt request ?g of an interrupt is fetched before the interrupt is generated, it is possible that the cpu might execute the fetched instruction to clear the interrupt request ?g while reading the interrupt vector after accepting the inter- rupt. if so, the cpu would read the default vector 00a0h and start the interrupt processing from the address 80a0h. to avoid this, make sure that the instruction used to clear the interrupt request ?g comes after the di instruction.
toshiba corporation 21 TMP96C141AF 3.4 standby function when the halt instruction is executed, the TMP96C141AF enters run, idle, or stop mode depending on the contents of the halt mode setting register. (1) run : only the cpu halts; power consumption remains unchanged. (2) idle : only the built-in oscillator operates, while all other built-in circuits halt. power consump- tion is reduced to 1/10 or less than that dur- ing normal operation. (3) stop : all internal circuits including the built-in oscil- lator halt. this greatly reduces power con- sumption. the states of the port pins in stop mode can be set as listed in table 3.4 (1) using the i/o register wdmodbit. 76543210 bit symbol wdte wdtp1 wdtp0 warm haltm1 haltm0 rescr drve read/write r/w after reset 10000000 function 1 : wdt enable 00 : 2 16 / fc 01 : 2 18 / fc 10 : 2 20 / fc 11 : 2 22 / fc detection time warming up time 0 : 2 16 /fc 1 : 2 18 /fc standby mode 00 : run mode 01 : stop mode 10 : idle mode 11 : don? care 1: connects watchdog timer output to reset pin internally. 1: drive pin even in stop mode. standby release by interrupt interrupt level standby mode interrupt mask (iff2 to 0) interrupt request level interrupt mask (iff2 to 0) > interrupt request level run can be released by any interrupt. after standby mode is released, interrupt processing starts. can only be released by int0 pin. processing resumes from address next to halt instruction. idle can only be released by nmi or int0 pin. after standby mode is released, interrupt processing starts. - stop - (note) - wdmod (005ch) when stop mode is released by other than a reset, the system clock output starts after allowing some time for warm- ing up set by the warming-up counter fro stabilizing the bulit-in oscillator. to release stop mode by reset, it is necessary to allow the oscillator to stabilize. to release standby mode, a reset or an interrupt is used. to release idle or stop mode, only an interrupt by the nmi or int0 pin, or a reset can be used. the details are described below:
22 toshiba corporation TMP96C141AF ? input for input mode/input pin is invalid; output mode/output pin is at high impedance. input: input enable state input: input gate in operation. fix input voltage to 0 or 1 so that input pin stays constant. output: output state pu: programmable pull-up pin. fix the pin to avoid through current since the input gate operates when a pull-up resistor is not set. pd: programmable pull-down pin. fix the pin like a pull-up pin when a pull-down resistor is not set. *: input gate disable state. no through current even if the pin is set to high impedance. x: cannot set. note: port registers are used for controlling programmable pull-up/pull-down. if a pin is also used for an output function (e.g., to1) and the output function is speci?d, whether pull-up or pull-down is selected depends on the output function data. if a pin is also used for an input function, whether pull-up or pull-down is selected depends on the port register setting value only. table 3. 4 (1) pin states in stop mode pin name i/o 96c141af 96cm40/96pm40 drve = 0 drve = 1 drve = 0 drve = 1 p0 input mode/ad0 ~ 7 output mode x x output p1 input mode/ad8 ~ 15 output mode/a8 ~ 15 x x output p2 input mode output mode/a0 ~ 7, a16 ~ 23 pd* pd* pd* output pd* pd* pd* output p30 (rd ), p31 (wr ) output ??output output p32 ~ p37 input mode output mode pu pu pu output ? p40, p41 input mode output mode pu* pu* pu output p42 (cs2 /cas2 ) input mode output mode pd* pd* pd output p5 input p6 input mode output mode pu* pu* pu output p7 input mode output mode pu* pu* pu output p80 ~ p86 input mode output mode pu* pu* pu output p87 (int0) input mode output mode pu pu pu output p9 input mode output mode pu* pu* pu output nmi input input input wdtout output output output ale output ? ? clk output ? reset input input input ea input input input x1 input x2 output ? ?
toshiba corporation 23 TMP96C141AF 15, rd , and wr . these port pins have i/o functions for the built-in cpu and internal i/os as well as general-purpose i/o port func- tions. table 3.5 lists the function of each port pin. (r: - = with programmable pull-up resistor = with programmable pull-down 3.5 functions of ports the tmp96cm40f/tmp96pm40f has 65 bits for i/o ports. the TMP96C141AF, tmp96c041af has 47 bits for i/o ports because port0, port1, p30, and p31 are dedicated pins for ad0 to 7, ad8 to table 3.5 functions of ports port name pin name number of pins direction r direction setting unit pin name for built-in function port0 p00 ~ p07 8 i/o bit ad0 ~ ad7 port1 p10 ~ p17 8 i/o bit ad8 ~ ad15/ a8 ~ a15 port2 p20 ~ p27 8 i/o bit a0 ~ a7/ a16 ~ a23 port 3 p30 p31 p32 p33 p34 p35 p36 p37 1 1 1 1 1 1 1 1 output output i/o i/o i/o i/o i/o i/o - - - - - - (fixed) (fixed) bit bit bit bit bit bit rd wr hwr w ait busrq busak r/w ras port4 p40 p41 p42 1 1 1 i/o i/o i/o - - bit bit bit cs0 / cas0 cs1 / cas1 cs2 / cas2 port5 p50 ~ p53 4 input (fixed) an0 ~ an3 port6 p60 ~ p67 8 i/o - bit pg00 ~ pg03, pg10 ~ pg13 port7 p70 p71 p72 p73 1 1 1 1 i/o i/o i/o i/o - - - - bit bit bit bit t10 to1 to2 to3 port8 p80 p81 p82 p83 p84 p85 p86 p87 1 1 1 1 1 1 1 1 i/o i/o i/o i/o i/o i/o i/o i/o - - - - - - - - bit bit bit bit bit bit bit bit t14/int4 t15/int5 to4 to5 t16 / int6 t17 / int7 to6 int0 port9 p90 p91 p92 p93 p94 p95 1 1 1 1 1 1 i/o i/o i/o i/o i/o i/o - - - - - - bit bit bit bit bit bit txd0 rxd0 cts0 txd1 rxd1 sclk1
24 toshiba corporation TMP96C141AF pin name pin state at bus release port mode function mode p00 - p07 (ad0 - ad7) p10 - p17 (ad8 - ad15) no status change (these pins are not ?z? these pins are ?z? p30 (rd ) p31 (wr ) - these pins are ?z? (?z?status after these pins are driven to high level.) p32 (hwr ) p37 (ras ) - the output buffer is ?ff?after these pins are drinen high. these pins are added in the internal resistor of pull-up. its no relation for the value of output latch. p36 (r/w ) p40 (cs0 /cas0 ) p41 (cs1 /cas1 ) -- p42 (cs2 /cas2 ) - (*) - p20 - p27 (a16 - a23) p42 (cs2 /cas2 ) - the output buffer is ?ff?after these pins are drinen high. these pins are added in the internal resistor of pull-down. its no relation for the value of output latch. (*) p42 has the resistor of programmable pull-down, but when the bus are released, p42 pin is added a resistor of pull- up. that is, when it is used for bus release (busak = ??, the pins of below need pull-up or pull-down resistor for an external circuit. p00 - p07 (ad07) p10 - p17 (ad8 - ad15) p30 (rd) p31 (wr) when the bus is released, both internal memory and internal i/o cannot be accessed. but the internal i/o continues to run. therefore, be careful about releasing time and set the setection time wdt. resetting makes the port pins listed below function as general-purpose i/o ports. i/o pins programmable for input or output function as input ports. to set port pins for built-in functions, a program is required. since the TMP96C141AF has an external rom, some ports are permanently assigned to the cpu. p00 ~ p07 ? ad0 ~ ad7 p10 ~ p17 ? ad8 ~ ad15 p30 ? rd p31 ? wr bus release function the TMP96C141AF has the internal pull-up and pull- down resistors to ? the bus control signals at bus release. table 3.5 (1) shows the pin condition at bus release (busak ) = ??. figure 3.5. example of external bus interface using bus release function.
toshiba corporation 25 TMP96C141AF 3.5.2 port 1 (p10 - p17) port 1 is an 8-bit general-purpose i/o port. i/o can be set on a bit basis using control register p1cr and function register p1fc. resetting resets all bits of output latch p1, control reg- ister p1cr, and function register p1fc to 0 and sets port 1 to input mode. in addition to functioning as a general purpose i/o port, port 1 also functions as an address data bus (ad8 to 15) or an address bus (a8 to 15). with the TMP96C141AF/tmp96c041af, which comes with an external rom, port 1 always functions as an address data bus (ad8 to 15) regardless of the value set in control reg- ister p1cr. 3.5.1 port 0 (p00 - p07) port 0 is an 8-bit general-purpose i/o port. i/o can be set on a bit basis using control register p0cr to 0 and sets port 0 to input mode. in addition to functioning as a general purpose i/o port, port 0 also functions as an address data bus (ad0 to 7). to access external memory, port 0 functions as an address data bus (ad 0 to 7) and all bits of the control register p0cr are cleared to 0. with the TMP96C141AF/tmp96c041af, which comes with an external rom, port 0 always functions as an address data bus (ad0 to 7) regardless of the value set in control regis- ter p0cr. figure 3.5 (1). port 0 figure 3.5 (2). port 1
26 toshiba corporation TMP96C141AF port 0 register figure 3.5 (3). registers for ports 0 and 1
toshiba corporation 27 TMP96C141AF 3.5.3 port 2 (p20 - p27) port 2 is an 8-bit general-purpose i/o port. i/o can be set on bit basis using the control register p2cr and function register p2fc. resetting resets all bits of output latch p2, control regis- ter p2cr and function register p2fc to 0. it also sets port 2 to input mode and connects a pull-down resistor. to disconnect the pull-down resistor, write 1 in the output latch. in addition to functioning as a general-purpose i/o port, port 2 also functions as an address data bus (a0 to 7) and an address bus (a16 to 23). figure 3.5 (4). port 2
28 toshiba corporation TMP96C141AF figure 3.5 (5). registers for port 2
toshiba corporation 29 TMP96C141AF 3.5.4 port 3 (p30 - p37) port 3 is an 8-bit general-purpose i/o port. i/o can be set on a bit basis, but note that p30 and p31 are used for output only. i/o is set using control register p3cr and function register p3fc. resetting resets all bits of output latch p3, control register p3cr (bits 0 and 1 are unused), and function register p3fc to 0. resetting also outputs 1 from p30 and p31, sets p32 to p37 to input mode, and connects a pull- up resistor. in addition to functioning as a general-purpose i/o port, port 3 also functions as an i/o for the cpus control/status sig- nal. with the TMP96C141AF, when p30 pin is de?ed as rd signal output mode ( = 1), clearing the output latch register to 0 outputs the rd strobe (used for the pseudo static ram) from the p30 pin even when the internal address area is accessed. if the output latch register remains 1, the rd strobe signal is output only when the external address area is accessed. with the TMP96C141AF/tmp96c041af, which comes with an external rom, port 30 outputs the rd signal; p31, the wr signal, regardless of the values set in function registers p30f and p31f.
30 toshiba corporation TMP96C141AF figure 3.5 (6). port 3 (p30, p31, p32, p35, p36, p37)
toshiba corporation 31 TMP96C141AF figure 3.5 (7). port 3 (p33, p34)
32 toshiba corporation TMP96C141AF port 3 register note: when p33/w ait pin is used as a w ait pin, set p#cr to ??and chip select/wait control register. figure 3.5 (8). registers for port 3
toshiba corporation 33 TMP96C141AF 3.5.5 port 4 (p40 - p42) port 4 is a 3-bit general-purpose i/o port. i/o can be set on a bit basis using control register p4cr and function register p4fc. resetting does the following: - sets the p40 and p42 output latch registers to 1. - resets all bits of the p42 output latch register, the control register p4cr, and the function register p4fc to 0. - sets p40 and p41 to input mode and connects a pull-up resistor. - sets p42 to input mode and connects a pull-down resistor. in addition to functioning as a general-purpose i/o port, port 4 also functions as a chip select output signal (cs0 to cs2 or cas0 to cas2 ).
34 toshiba corporation TMP96C141AF figure 3.5 (9). port 4
toshiba corporation 35 TMP96C141AF port 4 register note: to output chip select signal (cs0 /cas0 to cs2 /cas2 ), set the corresponding bits of the control register p4cr and the function register to p4fc. the bocs, b1cs, and b2cs registers of the chip select/wait controller are used to select the cs /cas function. figure 3.5 (10). registers for port 4
36 toshiba corporation TMP96C141AF 3.5.6 port 5 (p50 - p53) port 5 is a 4-bit input port, also used as an analog input pin. figure 3.5 (11). port 5 note: the input channel selection of a/d converter is set by a/d converter mode register admod2. figure 3.5 (12). registers for port 5 port 5 register 76543210 bit symbol p53 p52 p51 p50 read/write r after reset input mode p5 (000dh)
toshiba corporation 37 TMP96C141AF 3.5.7 port 6 (p60 - p67) port 6 is an 8-bit general-purpose i/o port. i/o can be set on bit basis. resetting sets port 6 as an input port and connects a pull-up resistor. it also sets all bits of the output latch to 1. in addition to functioning as a general-purpose i/o port, port 6 also functions as a pattern generator pg0/pg1 output. pg0 is assigned to p60 to p63; pg1, to p64 to p67. writing 1 in the corresponding bit of the port 6 function register (p6fc) enables pg output. resetting resets the function register p6fc value to 0, and sets all bits to ports. figure 3.5 (13). port 6
38 toshiba corporation TMP96C141AF port 6 register figure 3.5 (14). registers for port 6
toshiba corporation 39 TMP96C141AF 3.5.8 port 7 (p70 - p73) port 7 is a 4-bit general-purpose i/o port. i/o can be set on bit basis. resetting sets port 7 as an input port and connects a pull-up resistor. in addition to functioning as a general-purpose i/o port, port 70 also functions as an input clock pin ti0; port 71 as an 8-bit timer output (to1), port 72 as a pwm0 output (to2), and port 73 as a pwm1 output (to3) pin. writing 1 in the corresponding bit of the port 7 function register (p7fc) enables output of the timer. resetting resets the function regis- ter p7fc value to 0, and sets all bits to ports. figure 3.5 (15). port 7
40 toshiba corporation TMP96C141AF figure 3.5 (16). registers for port 7
toshiba corporation 41 TMP96C141AF 3.5.9 port 8 (p80 - p83) port 8 is an 8-bit general-purpose i/o port. i/o can be set on a bit basis. resetting sets port 8 as an input port and connects a pull-up resistor. it also sets all bits of the output latch register p8 to 1. in addition to functioning as a general-purpose i/o port, port 8 also functions as an input for 16-bit timer 4 and 5 clocks, an output for 16-bit timer f/f 4, 5 and 6 output, and an input for int0. writing 1 in the corresponding bit of the port 8 function register (p8fc) enables those functions. resetting resets the function register p8fc value to 0, and sets all bits to ports. (1) p80 ~ p86 figure 3.5 (17). port 8 (p80 - p86)
42 toshiba corporation TMP96C141AF (2) p87 (int0) port 87 is a general-purpose i/o port, and also used as an int0 pin for external interrupt request input. figure 3.5 (18). port 87
toshiba corporation 43 TMP96C141AF figure 3.5 (19). registers for port 8
44 toshiba corporation TMP96C141AF 3.5.10 port 9 (p90 - p95) port 9 is a 6-bit general-purpose i/o port. i/os can be set on a bit basis. resetting sets port 9 to an input port and connects a pull-up resistor. it also sets all bits of the output latch register to 1. in addition to functioning as a general-purpose i/o port, port 9 can also function as an i/o for serial channels 0 and 1. writing 1 in the corresponding bit of the port 9 function register (p9fc) enables this function. figure 3.5 (20). ports 90 and 93 resetting resets the function register value to 0 and sets all bits to ports. (1) port 90 and 93 (txd0/txd1) ports 90 and 93 also function as serial channel txd output pins in addition to i/o ports. they have a programmable open drain function.
toshiba corporation 45 TMP96C141AF (2) ports 91 and 94 (rxd0, 1) ports 91 and 94 are i/o ports, and also used as rxd input pins for serial channels. figure 3.5 (21). ports 91 and 94 (3) port 92 (cts/ sckl0) port 92 is an i/o port. it is also used as a cts input pin for serial channel0; additionally, the cts0 pin, and also as a sckl0 i/o pin. figure 3.5 (22). port 92
46 toshiba corporation TMP96C141AF (4) port 95 (sclk) port 95 is a general-purpose i/o port. it is also used as an sclk i/o pin for serial channel 1. figure 3.5 (23). port 95
toshiba corporation 47 TMP96C141AF figure 3.5 (24). registers for port 9
48 toshiba corporation TMP96C141AF 3.6 chip select/wait control TMP96C141AF has a built-in chip select/wait controller used to control chip select (cs0 - cs2 pins), wait (w ait pin), and data bus size (8 or 16 bits) for any of the three block address areas. 3.6.1 control registers table 3.6 (1) shows control registers one block address areas are controlled by 1-byte cs/ wait control registers (b0cs, b1cs, and b2cs). registers can be written to only when the cpu is in system mode. (there are two cpu modes: system and normal.) the reason is that the settings of these registers have an important effect on the system. (1) enable control register bit 7 (b0e, b1e, and b2e) is a master bit used to specify enable (1)/disable (0) of the setting. resetting b0e and b1e to disable (0) and b2e to enable (1). (2) system only speci?ation control register bit 6 (b0sys, b1sys, and b2sys) is used to specify enable/disable of the setting depend- ing on the cpu operating mode (system or normal). setting this bit to 0 enables setting (address space for cs , wait state, bus size, etc.) regardless of the cpu operating mode; setting it to 1 enables setting in sys- tem mode but disables setting in normal mode. resetting clears bit 6 to 0. bit 6 is mainly used when external memory data should not be accessed in normal mode (i.e., for system mode only memory data for the operating system). (3) cs/cas waveform select control register bit 5 (b0cas, b1cas, and b2cas) is used to specify waveform mode output from the chip select pin (cs0 /cas 0 - cs2 /cas2 ). setting this bit to 0 speci?s cs0 to cs2 waveforms; setting it to 1 speci?s cas0 to cas2 waveforms. resetting clears bit 5 to 0. (4) data bus size select bit 4 (b0bus, b1bus, and b2bus) of the control reg- ister is used to specify data bus size. setting this bit to 0 accesses the memory in 16-bit data bus mode; set- ting it to 1 accesses the memory in 8-bit data bus mode. changing data bus size depending on the access address is called dynamic bus sizing. table 3.6 (2) shows the details of the bus operation. (5) wait control control register bits 3 and 2 (b0w1, 0; b1w1, 0; b2w1, 0) are used to specify the number of waits. setting these bits to 00 inserts a 2-state wait regardless of the w ait pin status. setting them to 01 inserts a 1-state wait regardless of the w ait status. setting them to 10 inserts a 1-state wait and samples the w ait pin status. if the pin is low, inserting the wait maintains the bus cycle until the pin goes high. setting them to 11 com- pletes the bus cycle without a wait regardless of the w ait pin status. resetting sets these bits to 00 (2-state wait mode). (6) address area speci?ation control register bits 1 and 0 (b0c1, 0; b1c1, 0; b2c1, 0) are used to specify the target address area. setting these bits to 00 enables settings (cs output, wait state, bus size, etc.) as follows: * cs0 setting enabled when 7f00h to 7fffh is accessed. * cs1 setting enabled when 480h to 7fffh is accessed. * cs2 setting enabled when 8000h to 3ffffffh is accessed, for the tmp96c141, which does not have a built-in rom. cs2 setting enabled when 10000h to 3fffffh is accessed for the tmp96cm40/tmp96pm40, which has built-in rom/prom setting bits to 01 enables setting for all css blocks and outputs a low strobe signal (cs0 /cas0 ~ cs2 / cas2 ) from chip select pins when 400000h to 7fffffh is accessed. setting bits to 10 enables them 800000h to bfffffh is accessed. setting bits to 11 enables them when c00000h to ffffffh is accessed.
toshiba corporation 49 TMP96C141AF note: with only block 2, enable (16-bit data bus, 2-wait mode) after reset. table 3.6 (1) chip select/wait control register code name address 7654 3210 b0cs block0 cs/wait control register 0068h b0e b0sys b0cas b0bus b0w1 b0w0 b0c1 b0c0 wwww wwww 0000 0000 1 : cs/cas enable 1 : system only 0 : cso 1 : cas0 0 : 16-bit bus 1 : 8-bit bus 00 : 2wait 01 : 1wait 10 : 1wait + n 11 : 0wait 00 : 7f00h ~ 7fffh 01 : 400000h ~ 10 : 800000h ~ 11 : c00000h ~ b1cs block1 cs/wait control register 0069h b1e b1sys b1cas b1bus b1w1 b1w0 b1c1 b1c0 wwww wwww 0000 0000 1 : cs/cas enable 1 : system only 0 : cs1 1 : cas1 0 : 16-bit bus 1 : 8-bit bus 00 : 2wait 01 : 1wait 10 : 1wait + n 11 : 0wait 00 : 480h ~ 7fffh 01 : 400000h ~ 10 : 800000h ~ 11 : c00000h ~ b2cs block2 cs/wait control register 006ah b2e b2sys b2cas b2bus b2w1 b2w0 b2c1 b2c0 wwww wwww 1000 0000 1 : cs/cas enable 1 : system only 0 : cs2 1 : cas2 0 : 16-bit bus 1 : 8-bit bus 00 : 2wait 01 : 1wait 10 : 1wait +n 11 : 0wait 00 : 8000h ~ 01 : 400000h ~ 10 : 800000h ~ 11 : c00000h ~
50 toshiba corporation TMP96C141AF table 3.6 (2) dynamic bus sizing xxxxx: during a read, data input to the bus is ignored. at write, the bus is at high impedance and the write strobe signal remains non-active. operand data size operand start address memory data size cpu address cpu data d15 - d8 d7 - d0 8 bits 2n + 0 (even number) 8 bits 2n + 0 xxxxx b7 - b0 16 bits 2n + 0 xxxxx b7 - b0 2n + 1 (odd number) 8 bits 2n + 1 xxxxx b7 - b0 16 bits 2n + 1 b7 - b0 xxxxx 16 bits 2n + 0 (even number) 8 bits 2n + 0 2n + 1 xxxxx xxxxx b7 - b0 b15 - b8 16 bits 2n + 0 b15 - b8 b7 - b0 2n + 1 (odd number) 8 bits 2n + 1 2n + 2 xxxxx xxxxx b7 - b0 b15 - b8 16 bits 2n + 1 2n + 2 b7 - b0 xxxxx xxxxx b15 - b8 32 bits 2n + 0 (even number) 8 bits 2n + 0 2n + 1 2n + 2 2n + 3 xxxxx xxxxx xxxxx xxxxx b7 - b0 b15 - b8 b23 - b16 b31 - b24 16 bits 2n + 0 2n + 2 b15 - b8 b31 - b24 b7 - b0 b23 - b16 2n + 1 (odd number) 8 bits 2n + 1 2n + 2 2n + 3 2n + 4 xxxxx xxxxx xxxxx xxxxx b7 - b0 b15 - b8 b23 - b16 b31 - b24 16 bits 2n + 1 2n + 2 2n + 4 b7 - b0 b23 - b16 xxxxx xxxxx b15 - b8 b31 - b24
toshiba corporation 51 TMP96C141AF 3.6.2 chip select image an image of the actual chip select is shown below. out of the whole memory area, address areas that can be speci?d are divided into four parts. addresses from 000000h to 3fffffh are divided differently: 7f00h to 7fffh is speci?d for cs0; 480h to 7fffh, for cs1; and 8000h to 3fffffh, for cs2. the reason is that a device other than rom (i.e., ram or i/o) might be connected externally. the addresses 7f00 to 7fffh (256 bytes) for cs0 are mapped mainly for possible expansions to external i/o. the addresses 480h to 7fffh (approximately 31k supplement 1: access priority is highest for built-in i/o, then built-in memory, and lowest for the chip select/wait controller. supplement 2: external areas other than cs0 to cs2 are accessed in 16-bit data bus (0 wait) mode. when using the chip select/wait controller, do not specify the same address area more than once. (however, when addresses 7f00h - 7fffh for cs0 and 480h - 7fffh for cs1 are speci?d, in other words, speci?ations overlap, only the cs0 setting/pin is active.) cs0 cs1 cs2 000000h 7f00h b1c1, 0 = ?0 8000h b0c1, 0 = ?0 400000h b2c1, 0 = ?0 800000h b0c1, 0 = ?1 b1c1, 0 = ?1 b2c1, 0 = ?1 c00000h b0c1, 0 = ?0 b1c1, 0 = ?0 b2c1, 0 = ?0 ffffffh b0c1, 0 = ?1 b1c1, 0 = ?1 b2c1, 0 = ?1 (mainly for i/o) (mainly for ram) (mainly for rom) bytes) for cs1 are mapped there mainly for possible exten- sions to external ram. the addresses 8000h to 3ffffffh (approximately 4mbytes) for cs2 are mapped mainly for possible extensions to external rom. after reset, cs2 is enabled in 16-bit bus and 2-wait. with the TMP96C141AF, which does not have a built- in rom, the program is externally read at address 8000h in this setting (16-bit bus, 2-wait). with the tmp96cm40f/ tmp96pm40f, which has a built-in rom, addresses from 8000h to fffffh are used as the internal rom area; cs2 is disabled in this area. after reset, the cpu reads the program from the built-in rom in 16-bit bus, 0-wait mode.
52 toshiba corporation TMP96C141AF 3.6.3 example of usage figure 3.6 (1) is an example in which an external memory is con- nected to the TMP96C141AF. in this example, a rom is con- nected using 16-bit bus; a ram is connected using 8-bit bus. figure 3.6 (1). example of external memory connection (rom = 16 bits, ram and i/o = 8 bits) resetting sets pins cs0 to cs2 to input port mode. cs0 and cs1 are set high due to an internal pull-up resistor; cs2 , low due to an internal pull-down resistor. the program used to set these pins is as follows: p4cr equ 0eh p4fc equ 10h b0cs equ 68h b1cs equ 69h b2cs equ 6ah ld (bocs), 90h ; cs0 = 8 bits, 2wait, 7f00h ~ 7fffh ld (b1cs), 9ch ; cs1 = 8 bits, 0wait, 480h ~ 7effh ld (b2cs), 84h ; cs2 = 16 bits, 1wait, 8000h ~ 3fffffh ld (p4cr), 07h ld (p4fc), 07h ) cso , cs1 , cs2 output mode setting
toshiba corporation 53 TMP96C141AF 3.6.4 how to start with an 8-bit data bus resetting sets the cs2 pin low due to an internal pull-down resistor; memory access starts in 16-bit data bus (2-wait) mode. to start in 8-bit data bus mode, a special operation is required. operation is as described in the example below: b2cs equ 6ah ; cs2 register address org 8000h ; reset address ldx (b2cs), 9ch ; cs2 8-bit, 0wait, 8000h ~ after reset, the program reads the ldx (b2cs), 9ch instruction in 16-bit data bus mode. ldx is a 6-byte instruc- tion: the 2nd, 4th and 6th bytes are handled as dummies (i.e., only codes in the 1st, 3rd and 5th bytes are actually used). even if starting in 8-bit data bus mode, it is possible to pro- gram so that the ldx instruction is executed and the block 2 area (8000h - 3fffffh) is accessed in 8-bit data bus mode without any problem. the above program does not include setting the p42/ cs2 pin to output; add a program to set the p4cr and p4fc registers as required.
54 toshiba corporation TMP96C141AF 3.7 8-bit timers the TMP96C141AF contains two 8-bit timers (timers 0 and 1), each of which can be operated independently. the cascade connection allows these timers to be used as 16-bit timer. the following four operating modes are provided for the 8-bit tim- ers. 8-bit interval timer mode (2 timers) 16-bit interval timer mode (1 timer) 8-bit programmable square wave pulse generation (ppg : variable duty with variable cycle) output mode (1 timer) 8-bit pulse width modulation (pwm: variable duty with con- stant cycle) output mode (1 timer) figure 3.7 (1) shows the block diagram of 8-bit timer (timer 0 and timer 1). each interval timer consists of an 8-bit up-counter, 8-bit comparator, and 8-bit timer register. besides, one timer ?p- ?p (tff1) is provided for pair of timer 0 and timer 1. among the input clock sources for the interval timers, the internal clocks of f t1, f t4, f t16, and f t256 are obtained from the 9-bit prescaler shown in figure 3.7 (2). the operation modes and timer ?p-?ps of the 8-bit timer are controlled by three control registers tmod, tffcr, and trun.
toshiba corporation 55 TMP96C141AF figure 3.7 (1). block diagram of 8-bit timers (timers 0 and 1)
56 toshiba corporation TMP96C141AF prescaler this 9-bit prescaler generates the clock input to the 8- bit timers, 16-bit timer/event counters, and baud rate generators by further dividing the fundamental clock (fc) after it has been divided by 4 (fc/4). among them, 8-bit timer uses four types of clock: f t1, f t4, f t16, and f t256. this prescaler can be run or stopped by the timer operation control register trun . counting starts when is set to ?? while the prescaler is cleared to zero, and stops operation when is set to ?? resetting clears to ?? which clears and stops the prescaler. up-counter this is an 8-bit binary counter which counts up by the input clock pulse speci?d by tmod. the input clock of timer 0 is selected from the external clock from t10 pin and the three internal clocks f t1 (8/fc), f t4 (32/fc), and f t16 (128/fc), according to the set value of tmod register. the input clock of timer 1 differs depending on the operation mode. when set to 16-bit timer mode, the over?w output of timer 0 is used as the input clock. when set to any other mode than 16-bit timer mode, the input clock is selected from the internal clocks f t1 (8/fc), f t16 (128/fc), and f t256 (2048/fc) as well as the comparator output (match detection signal) of timer 0 according to the set value of tmod register. example : when tmod = 01, the over ?w output of timer 0 becomes the input clock of timer 1 (16 bit timer mode). when tmod = 00 and tmod = 01, f t1 (8/fc) becomes the input of timer 1 (8 bit timer mode). operation mode is also set by tmod register. when reset, it is initialized to tmod = 00 whereby the up-counter is placed in the 8-bit timer mode. the counting and stop and clear of up-counter can be controlled for each interval timer by the timer operation control register trun. when reset, all up-counters will be cleared to stop the timers. figure 3.7 (2). prescaler
toshiba corporation 57 TMP96C141AF a timer register this is an 8-bit register for setting an interval time. when the set value of timer registers treg0, treg1, matches the value of up-counter, the comparator match detect signal becomes active. if the set value is 00h, this signal becomes active when the up-counter over?ws. timer register treg0 is of double buffer structure, each of which makes a pair with register buffer. the timer ?p-?p control register tffcr bit controls whether the double buffer structure in the figure 3.7 (3). con?uration of timer register 0 note : timer register and the register buffer are allocated to the same memory address. when = 0, the same value is written in the register buffer as well as the timer register, while when = 1 only the register buffer is written. treg0 should be enabled or disabled. it is disabled when = 0 and enabled when they are set to 1. in the condition of double buffer enable state, the data is transferred from the register buffer to the timer regis- ter when the 2 n -1 over?w occurs in pwm mode, or at the ppg cycle in ppg mode. therefore, during timer mode, the double buffer cannot be used. when reset, it will be initialized to = 0 to dis- able the double buffer. to use the double buffer, write data in the timer register, set to 1, and write the following data in the register buffer. the memory address of each timer register is as fol- lows. treg0: 000022h treg1: 000023h all registers are write-only and cannot be read. ? comparator a comparator compares the value in the up-counter with the values to which the timer register is set. when they match, the up-counter is cleared to zero and an interrupt signal (intt0, intt1) is generated. if the timer ?p-?p inversion is enabled, the timer ?p-?p is inverted at the same time. timer flip-flop (timer f/f: tff1) the status of the timer ?p-?p is inverted by the match detect signal (comparator output) of each interval timer and the value can be output to the timer output pins to1 (also used as p71). a timer f/f is provided for a pair of timer 0 and timer 1 and is called tff1. tff1 is output to to1 pin.
58 toshiba corporation TMP96C141AF figure 3.7 (4). timer operation control register (trun)
toshiba corporation 59 TMP96C141AF figure 3.7 (5). timer mode control register (tmod)
60 toshiba corporation TMP96C141AF figure 3.7 (6). timer flip-flop control register (tffcr)
toshiba corporation 61 TMP96C141AF the operation of 8-bit timers will be described below: (1) 8-bit timer mode two interval timers 0, 1, can be used independently as 8-bit interval timer. all interval timers operate in the same manner, and thus only the operation of timer 1 will be explained below. note: x; dont care ? no change use the following table for selecting the input clock. note: the input clock of timer 0 and timer 1 are different from as follows: timer 0: t10 input, f t1, f t4, f t16 timer 1: match output of timer 0, f t1, f t16, f t256 msb lsb 76543210 trun ? 0 stop timer 1, and clear it to ?? tmod 0 0 x x 0 1 set the 8-bit timer mode, and select f t1 (0.5 m s @ fc = 16mhz) as the input clock. treg1 01010000 set the timer register at 40 m s f t1 = 50h. intet10 1101 enable intt1, and set it to ?evel 5? trun 1x 1 start timer 1 counting. table 3.7 (1) 8-bit timer interrupt cycle and input clock input clock interrupt cycle (at fc = 16mhz) resolution interrupt cycle (at fc = 20mhz) resolution f t1 (8/fc) 0.5 m s ~ 128 m s 0.5 m s 0.4 m s ~ 102.4 m s 0.4 m s f t4 (32/fc) 2 m s ~ 512 m s2 m s 1.6 m s ~ 409.6 m s 1.6 m s f t16 (128/fc) 8 m s ~ 2.048ms 8 m s 6.4 m s ~ 1.638ms 6.4 m s f t256 (2048/fc) 128 m s ~ 32.708ms 128 m s 102.4 m s ~ 2.621ms 128 m s generating interrupts in a fixed cycle to generate timer 1 interrupt at constant intervals using timer 1 (intt1), ?st stop timer 1 then set the operation mode, input clock, and a cycle to tmod and treg1 register, respectively. then, enable interrupt intt1 and start the counting of timer 1. example: to generate timer 1 interrupt every 40 microseconds at fc = 16 mhz, set each register in the following manner.
62 toshiba corporation TMP96C141AF generating a 50% duty square wave pulse the timer ?p-?p (tff1) is inverted at constant inter- vals, and its status is output to timer output pin (to1). example: to output a 3.0 m s square wave pulse from to1 pin at fc = 16mhz, set each register in the following procedures. either timer 0 or timer 1 may be used, but this example uses timer 1. note: x; dont care ? no change figure 3.7 (7). square wave (50% duty) output timing chart 76543210 trun ? 0 stop timer 1, and clear it to ?? tmod 0 0 x x 0 1 set the 8-bit timer mode, and select f t1 (0.5 m s @ fc = 16mhz) as the input clock. treg1 00000011 set the timer register at 3.0 m s f t1 2 = 3. tffcr 1011 clear tff1 to ?? and set to invert by the match detect signal from timer 1. p7cr xxxx1 p7fc xxxx1x trun 1x 1 start timer 1 counting. ) select p71 as to1 pin.
toshiba corporation 63 TMP96C141AF a making timer 1 count up by match signal from timer 0 comparator set the 8-bit timer mode, and set the comparator out- put of timer 0 as the input clock to timer 1. figure 3.7 (8). timer 1 count up by timer 0 ? output inversion with software the value of timer ?p-?p (tff1) can be inverted, inde- pendent of timer operation. writing ?0?into tffcr (memory address: 000025h of bit 3 and bit 2) inverts the value of tff1. ? initial setting of timer flip-flop (tff1) the value of tff1 can be initialized to ??or ?? inde- pendent of timer operation. for example, write ?0?in tffcr to clear tff1 to ?? while write ?1?in tffcr to set tff1 to ?? table 3.7 (2) 16-bit timer (interrupt) and input clock input clock interrupt cycle (at fc = 16mhz) resolution interrupt cycle (at fc = 20mhz) resolution f t1 (8/fc) 0.5 m s ~ 32.786ms 0.5 m s 0.4 m s ~ 26.214ms 0.4 m s f t4 (32/fc) 2 m s ~ 131.072ms 2 m s 1.6 m s ~ 104.857ms 1.6 m s f t16 (128/fc) 8 m s ~ 524.288ms 8 m s 6.4 m s ~ 419.430ms 6.4 m s note: the value of timer register cannot be read. (2) 16-bit timer mode a 16-bit interval timer is con?ured by using the pair of timer 0 and timer 1. to make a 16-bit interval timer by cascade connecting timer 0 and timer 1, set timer 0/timer 1 mode register tmod to ?, 1? when set in 16-bit timer mode, the over?w output of timer 0 will become the input clock of timer 1, regard- less of the set value of tmod . table 3.7 (2) shows the relation between the cycle of timer (inter- rupt) and the selection of input clock.
64 toshiba corporation TMP96C141AF the lower 8 bits of the timer (interrupt) cycle are set by the timer register treg0, and the upper 8 bits are set by treg1. note that treg0 always must be set ?st. (writing data into treg0 disables the comparator tem- porarily, and the comparator is restarted by writing data into treg1.) setting example: to generate an interrupt intt1 every 0.5 seconds at fc = 16mhz, set the following values for timer registers treg0 and treg: when counting with input clock of f t16 (8 m s @ 16mhz) 0.5 sec 8 m s = 62500 = f424h therefore, set treg1 = f4h and treg0 = 24h, respectively. the comparator match signal is output from timer 0 each time the up-counter uc0 matches treg0, where the up-counter uc0 is not to be cleared. with the timer 1 comparator, the match detect signal is output at each comparator timing when up-counter uc1 and treg1 values match. when the match detect signal is output simultaneously from both com- parators of timer 0 and timer 1, the up-counters uc0 and uc1 are cleared to ?? and the interrupt intt1 is generated. if inversion is enabled, the value of the timer ?p-?p tff1 is inverted. example: when treg1 = 04h and treg0 = 80h figure 3.7 (9). output timer by 16-bit timer mode (3) 8-bit ppg (programmable pulse generation) output mode square wave pulse can be generated at any frequency and duty by timer 0 and timer 1. the output pulse may be either low-active or high-active. in this mode, timer 1 cannot be used. timer 0 outputs pulse to to1 pin (also used as p70). in this mode, a programmable square wave is gener- ated by inverting timer output each time the 8-bit up- counter (uc0) matches the timer registers treg0 and treg1. however, it is required that the set value of treg0 is smaller than that of treg1. though the up-counter (uc1) of timer 1 is not used in this mode, uc1 should be set for counting by setting trun to 1. figure 3.7 (11) shows the block diagram for this mode.
toshiba corporation 65 TMP96C141AF figure 3.7 (10). 8-bit ppg output waveforms figure 3.7 (11). block diagram of 8-bit ppg output mode
66 toshiba corporation TMP96C141AF when the double buffer of treg0 is enabled in this mode, the value of register buffer will be shifted in treg0 each time treg1 matches uc0. use of the double buffer makes easy handling of low duty waves (when duty is varied). figure 3.7 (12). operation of register buffer example: generating 1/4 duty 50khz pulse @ fc = 16mhz) calculate the value to be set for timer register. to obtain the frequency 50khz, the pulse cycle t should be: t = 1/50khz = 20 m s. given f t1 = 0.5 m s @ 16mhz), 20 m s 0.5 m s = 40 consequently, to set the timer register 1 (treg1) to treg1 = 40 = 28h and then duty to 1/4, t x 1/4 = 20 m s x 1/4 = 5 m s 5 m s 0.5 m s = 10 therefore, set timer register 0 (treg0) to treg0 = 10 = 0ah. note : x; dont care ? no change 76543210 trun ? 00 stop timer 0, and clear it to ?? tmod 10xxxx01 set the 8-bit ppg mode, and select f t1 as input clock. treg0 00001010 write ?ah? treg1 00101000 write ?8h? tffcr 1011x sets tff1 and enables the inversion and double buffer enable. writing ?0?provides negative logic pulse. p7cr xxxx1 p7fc xxxx1x trun 1x 11 start timer 0 and timer 1 counting. ) set p71 as to1 pin.
toshiba corporation 67 TMP96C141AF (4) 8-bit pwm output mode this mode is valid only for timer 0. in this mode, maxi- mum 8-bit resolution of pwm pulse can be output. pwm pulse is output to to1 pin (also used as p71) when using timer 0. timer 1 can also be used as 8-bit timer. timer output is inverted when up-counter (uc0) matches the set value of timer register treg0 or when 2n - 1 (n = 6, 7, or 8; speci?d by t01mod ) counter over?w occurs. up-counter uc0 is cleared when 2n - 1 counter over?w occurs. for example, when n = 6, 6-bit pwm will be output, while when n = 7, 7-bit pwm will be output. to use this pwm mode, the following conditions must be satis?d. (set value of timer register) <(set value of 2 n - 1 counter over?w) (set value of timer register 0)
68 toshiba corporation TMP96C141AF figure 3.7 (14) shows the block diagram of this mode. figure 3.7 (14). block diagram of 8-bit pwm mode in this mode, the value of register buffer will be shifted in treg0 if 2 n - 1 over?w is detected when the double buffer of treg0 is enabled. use of the double buffer makes the handling of small duty waves easy. figure 3.7 (15). operation of register buffer example: to output the following pwm waves to to1 pin at fc = 16mhz. to realize 63.5 m s of pwm cycle by f t1 = 0.5 m s (@ fc = 16mhz), 63.5 m s 0.5 m s = 127 = 2 7 - 1 consequently, n should be set to 7. as the period of low level is 36 m s, for f t1 = 0.5 m s, set the following value for treg0: 36 m s 0.5 m s = 72 = 48h
toshiba corporation 69 TMP96C141AF note: x; dont care ? no change (5) table 3.7 (4) shows the list of 8-bit timer modes. note: ? dont care msb lsb 76543210 trun - x ? stop timer 0, and clear it to ?? tmod 111001 set 8-bit pwm mode (cycle: 2 7 - 1) and select f t1 as the input clock. treg0 01001000 write ?8h? tffcr xxxx 101x clears tff1, enables the inversion and double buffer. p7cr xxxx1 p7fc xxxx1x trun 1x ? start timer 0 counting. table 3.7 (3) pwm cycle and the setting of 2 n -1 counter pwm cycle (@ fc =16mhz) pwm cycle (@ fc = 20 mhz) f t1 f t4 f t16 f t1 f t4 f t16 2 6 -1 31.5 m sec (31.7khz) 126msec (7.9khz) 0.50 m sec (1.9khz) 25.2 m sec (39.0khz) 100 m sec (10.0khz) 0.40msec (2.4khz) 2 7 -1 63.5 m sec (15.7khz) 254msec (3.9khz) 1.01 m sec (0.98khz) 50.8 m sec (19.7khz) 203 m sec (4.9khz) 0.81msec (1.2khz) 2 8 -1 127 m sec (7.8khz) 510msec (1.9khz) 2.04 m sec (0.49khz) 102 m sec (9.80khz) 408 m sec (2.4khz) 1.63msec (0.61khz) table 3.7 (4) timer mode setting registers register name tmod tffcr name of function in t10m pwmm t1clk t0clk tff1is function timer mode pwm0 cycle upper timer input clock lower timer input clock timer f/f invert signal select 16-bit timer mode 01 external clock, f t1, f t4, f t16 (00, 01, 10, 11) 8-bit timer x 2 channels 00 lower timer match : f t1, f t16, f t256 (00, 01, 10, 11) external clock, f t1, f t4, f t16 (00, 01, 10, 11) 0 : lower timer output 1 : upper timer output 8-bit ppg x 1 channel 10 external clock, f t1, f t4, f t16 (00, 01, 10, 11) 8-bit pwm x 1 channel 11 2 6 - 1, 2 7 - 1, 2 8 - 1 (01, 10, 11) external clock, f t1, f t4, f t16 (00, 01, 10, 11) 8-bit timer x 1 channel 11 f t1, f t16, f t256 (01, 10, 11) output disabled ) set p71 as the to1 pin.
70 toshiba corporation TMP96C141AF 3.8 8-bit pwm timer the TMP96C141AF/tmp96cm40f/tmp96pm40f has two built-in 8-bit pwm timers (timers 2 and 3). they have two operating modes. 8-bit pwm (pulse width modulation: variable duty at fixed interval) output mode 8-bit interval timer mode figure 3.8 (1) is a block diagram of 8-bit pwm timer (tim- ers 2 and 3). pwm timers consist of an 8-bit up-counter, 8-bit com- parator, and 8-bit timer register. two timer ?p-?ps (tff2 for timer 2 and tff3 for timer 3) are provided. input clocks f p1, f p4, and f p16 for the pwm timers can be obtained using the built-in prescaler. pwm timer operating mode and timer ?p-?ps are con- trolled by four control registers (p0mod, p1mod, pffcr, and trun).
toshiba corporation 71 TMP96C141AF figure 3.8 (1). block diagram of 8-bit pwm timer 0 (timer 2) note: block diagram for 8-bit pwm timer 1 (timer 3) is the same as the above diagram.
72 toshiba corporation TMP96C141AF prescaler generates input clocks dedicated to pwm timers by further dividing the fundamental clock (fc) after it has been divided by 2 (fc/2). since the register used to control the prescaler is the same as the one for other timers, the prescaler cannot be operated indepen- dently. the pwm timer uses three input clocks: f /p1, f /p4, and f /p16. like the 9-bit prescaler described in the 8-bit timer section, this prescaler can be counted/stopped using bit 7 of the timer operation control register trun. setting to 1 starts counting; setting it to 0 zero-clears and stops counting. resetting clears to 0, which clears and stops the prescaler. figure 3.8 (2). prescaler dedicated prescaler cycle 16mhz 20mhz f p1 (4/fc) 250ns 200ns f p4 (16/fc) 1 m s 800ns f p16 (64/fc) 4 m s 3.2 m sc up-counter an 8-bit binary counter which counts up using the input clock speci?d by pwm mode register (p0mod or p1mod). the input clock for the pwm0/pwm1 is selected from the internal clocks f p1, f p4, and f p16 (pwm dedi- cated prescaler output) depending on the value set in the p0mod/p1mod register. operating mode is also set by p0mod and p1mod registers. at reset, they are initialized to p0mod = 0 and p1mod = 0, thus, the up-counter is in pwm mode. in pwm mode, the up- counter is cleared when a 2 n - 1 over?w occurs; in timer mode, the up-counter is cleared at compare and match. count/stop and clear of the up-counter can be con- trolled for each pwm timer using the timer operation control register trun. resetting clears all up-counters and stops timers. a timer registers two 8-bit registers used for setting an interval time. when the value set in the timer registers (treg 2 and 3) matches the value in the up-counter, the match detect signal of the comparator becomes active. timer registers treg2 and treg3 are each paired with register buffer to make a double buffer structure.
toshiba corporation 73 TMP96C141AF treg2 and treg3 are controlled double buffer enable/disable by p0mod and p1mod : disabled when / = 0, enabled when / = 1. data is transferred from register buffer to timer when a 2 n - 1 over?w occurs in the pwm mode, or when compare and match occurs in 8-bit timer mode. that is, with a pwm timer, the timer mode can be operated figure 3.8 (3). structure of timer registers 2 and 3 in double buffer enable state, unlike timer mode for timers 0 and 1. at reset, / is initialized to 0 to dis- able double buffer. to use double buffer, write the data in the timer register at ?st, then set / to 1, and write the following data in the reg- ister buffer. note: the timer register and register buffer are allocated to the same memory address. when / = 0, the same value is written to both register buffer and timer register. when / = 1, the value is written to the register buffer only. memory addresses of the timer registers are as follows: treg2 : 000026h treg3 : 000027h both timer registers are write only; however, register buffer values can be read when reading the above addresses. ? comparator compares the value in the up-counter with the value in the timer register (treg2/treg3). when they match, the comparator outputs the match detect signal. a timer interrupt (intt2/intt3) is generated at compare and match if the interrupt select bit / of the mode register (p0mod/p1mod) is set to 1. in timer mode, the comparator clears the up- counter to 0 at compare and match. it also inverts the value of the timer ?p-?p if timer ?p-?p invert is enabled. ? timer flip-flop the value of the timer ?p-?p is inverted by the match detect signal (comparator output) of each interval timer or 2 n - 1 over?w. the value can be output to the timer output pin to2/to3 (also used as p72/p73).
74 toshiba corporation TMP96C141AF figure 3.8 (4). 8-bit pwm0 mode control register
toshiba corporation 75 TMP96C141AF figure 3.8 (5). 8-bit pwm1 mode control register
76 toshiba corporation TMP96C141AF figure 3.8 (6). 8-bit pwm f/f control register
toshiba corporation 77 TMP96C141AF figure 3.8 (7). timer operation control register (trun)
78 toshiba corporation TMP96C141AF the following explains pwm timer operations. (1) pwm timer mode both pwm timers can output 8-bit resolution pwm independently. since both timers operate in exactly the same way, pwm0 is used for purposes of explanation. pwm output changes under the following two condi- tions. condition 1: tff2 is cleared to 0 when the value in the up- counter (uc2) and the value set in the treg2 match. tff2 is set to 1 when a 2 n - 1 counter over?w (n = 6, 7, or 8) occurs. pwm timing figure 3.8 (8). output waves in pwm timer mode note: the above waves are obtained in a mode where the f/f is set by a match with the timer register (treg) and reset by an over?w. condition 2: tff2 is set to 1 when the value in the up-counter (uc2) and the value set in treg2 match. tff2 is cleared to 0 when a 2 n - 1 counter over ?w (n = 6, 7, or 8) occurs. the up-counter (uc2) is cleared by a 2 n - 1 counter over?w. the pwm timer can output 0% - 100% duty pulses because a 2 n - 1 counter over?w has a higher priority. that is, to obtain 0% output (always low), the mode used to set tff2 to 0 due to over?w (pffcr = 1, 0) must be set and 2 n - 1 (value for over?w) must be set in treg2. to obtain 100% out- put (always high), the mode must be changed: pffcr = 1,1 then the same operation is required.
toshiba corporation 79 TMP96C141AF figure 3.8 (9) is a block diagram of this mode. figure 3.8 (9). block diagram of pwm timer mode (pwm0) in this mode, enabling double buffer is very useful. the register buffer value shifts into treg2 when a 2 n -1 over?w is detected, when double buffer is enabled. using double buffer makes handling small duty waves easy. figure 3.8 (10). register buffer operation
80 toshiba corporation TMP96C141AF example: to output the following pwm waves to to2 pin using pwm0 at fc = 16mhz. to implement 31.75 m s pwm cycle by f p1 = 0.25 m s (@ fc = 16mhz) 31.75 m s 0.25 m s = 127 = 2 7 -1. consequently, set n to 7. since the low level cycle = 15 m s; for f p1 = 0.25 m s 15 m s 0.25 = 60 = 3ch set the 3ch in treg2. note: x; dont care ? no change 76543210 trun ? ? stops pwm0 and clears it to 0. p0mod - 0000001 sets pwm (2 7 - 1) mode, input clock f p1, over?w interrupt, and disables double buffer. treg2 00111100 writes 3ch. p0mod 1000001 enables double buffer. pffcr 0111 sets tff2 and a mode where tff2 is set by compare and match, and cleared by over?w. p7cr xxxx1 p7fc xxxx1x trun 1x ? starts pwm0 counting. table 3.8 (1) pwm cycle and 2 n -1 counter setting formula 16mhz 20mhz f p1 f p4 f p16 f p1 f p4 f p16 2 6 -1 2 6 -1 - f pn 15.8 m sec (63khz) 63.0 m sec (16khz) 252 m sec (3.9khz) 12.6 m sec (79khz) 50.4 m sec (20khz) 201 m sec (4.9khz) 2 7 -1 2 7 -1 - f pn 31.8 m sec (31khz) 127.0 m sec (7.9khz) 508 m sec (1.9khz) 25.4 m sec (39khz) 101.6 m sec (9.8khz) 406 m sec (2.5khz) 2 8 -1 2 8 -1 - f pn 63.8 m sec (16khz) 255.0 m sec (3.9khz) 1020 m sec (0.98khz) 51.0 m sec (20khz) 204.0 m sec (4.9khz) 816 m sec (1.2khz) ) sets p72 as the to2 pin.
toshiba corporation 81 TMP96C141AF (2) 8-bit timer mode both pwm timers can be used independently as 8-bit interval timers. since both timers operate in exactly the same way, pwm0 (timer 2) is used for the purposes of explanation. note: x; dont care ? no change select an input clock using the table below. note: to generate interrupts in 8-bit timer mode, bit 5 (interrupt control bit / of p0mod/p1mod) must be set to 1. 76543210 trun ? ? stops pwm0 and clears it to 0. p0mod x01100xx sets 8-bit timer mode and selects f p1 (0.25 m s) and compare interrupt. treg2 10100000 sets 40 m s/0.25 m s = a0h in timer register. intepw10 1100 enables intt2 and sets interrupt level 4. trun 1x ? starts pwm0 counting. table 3.8 (2) interrupt cycle and input clock selection using 8-bit timer mode input clock interrupt cycle (at fc = 16mhz) resolution interrupt cycle (at fc = 20mhz) resolution f p1 (4/fc) 0.25 m s ~ 64 m s 0.25 m s 0.2 m s ~ 51.2 m s 0.2 m s f p4 (16/fc) 1 m s ~ 256 m s1 m s 0.8 m s ~ 204.8 m s 0.8 m s f p16 (64/fc) 4 m s ~ 1024 m s4 m s 3.2 m s ~ 819.2 m s 3.2 m s generating interrupts at a fixed interval to generate timer 2 interrupt (intt2) at a ?ed interval using pwm0 timer, ?st stop pwm0, then set the oper- ating mode, input clock, and interval in the p0mod and treg2 registers. next, enable intt2 and start counting pwm0. example: to generate a timer 2 interrupt every 40 m s at fc = 16mhz, set registers as follows:
82 toshiba corporation TMP96C141AF generating a 50% square wave to generate a 50% square wave, invert the timer ?p- ?p at a ?ed interval and output the timer ?p-?p value to the timer output pin (to2). example: to output a 3.0 m s square wave at fc = 16mhz from to2 pin, set register as fol- lows: note: x; dont care ? no change figure 3.8 (11). square wave (50% duty) output timing chart 76543210 trun ? ? stops pwm0 and clears it to 0. p0mod x01100xx sets 8-bit timer mode and selects f p1 (0.25 m s) as the input clock. treg2 00000110 sets 3.0 m s/0.25 m s/2 = 6 in the timer register. pffcr 1001 clears tff2 to 0 and inverts using comparator output. p7cr xxxx1 p7fc xxxx1x trun 1x ? ) sets p72 as the to2 pin.
toshiba corporation 83 TMP96C141AF this mode is as shown in figure 3.8 (12) below. figure 3.8 (12). block diagram of 8-bit timer mode
84 toshiba corporation TMP96C141AF 3.9 16-bit timer the TMP96C141AF has two (timer 4 and timer 5) multifunc- tional 16-bit timer/event counter with the following operation modes. 16-bit interval timer mode 16-bit event counter mode 16-bit programmable pulse generation (ppg) mode frequency measurement mode pulse width measurement mode time differential measurement mode timer/event counter consists of 16-bit up-counter, two 16-bit timer registers, two 16-bit capture registers (one of them applies double-buffer), two comparators, capture input con- troller, and timer ?p-?p and the control circuit. timer/event counter is controlled by four control regis- ters: t4mod/t5mod, t4ffcr/t5ffcr, trun and t45cr. figure 3.9 (1) and (2) show the block diagram of 16-bit timer/event counter (timer 4 and timer 5).
toshiba corporation 85 TMP96C141AF figure 3.9 (1). block diagram of 16-bit timer (timer 4)
86 toshiba corporation TMP96C141AF figure 3.9 (2). block diagram of 16-bit timer (timer 5)
toshiba corporation 87 TMP96C141AF figure 3.9 (3). 16-bit timer mode controller register (t4mod) (1/2)
88 toshiba corporation TMP96C141AF figure 3.9 (4). 16-bit controller register (t4mod) (2/2)
toshiba corporation 89 TMP96C141AF figure 3.9 (5). 16-bit timer 4 f/f control (t4ffcr)
90 toshiba corporation TMP96C141AF figure 3.9 (6). 16-bit timer mode control register (t5mod) (1/2)
toshiba corporation 91 TMP96C141AF figure 3.9 (7). 16-bit timer control register (t5mod) (2/2)
92 toshiba corporation TMP96C141AF figure 3.9 (8). 16-bit timer 5 f/f control (t5ffcr) cap4t6 : invert when the up-counter value is loaded to cap4 cap3t6 : invert when the up-counter value is loaded to cap3 eq7t6 : invert when up-counter matches treg7 eq6t6 : invert when up-counter matches treg6
toshiba corporation 93 TMP96C141AF figure 3.9 (9). 16-bit timer (timer 4, 5) control register (t45cr) figure 3.9 (10). timer operation control register (trun) db6en : double buffer of treg6 db4en : double buffer of treg4
94 toshiba corporation TMP96C141AF up-counter (uc4/uc5) uc4/uc5 is a 16-bit binary counter which counts up according to the input clock speci?d by t4mod or t5mod register. as the input clock, one of the internal clocks f t1 (8/ fc), f t4 (32/fc), and f t16 (128/fc) from 9-bit prescaler (also used for 8-bit timer), and external clock from ti4 pin (also used as p80/int4 pin) or ti6 (also used as p84/ int6 pin) can be selected. when reset, it will be initialized to / = 00 to select ti4/ti6 input mode. counting or stop and clear of the counter is controlled by timer operation control register trun . when clearing is enabled, up-counter uc4/uc5 will be cleared to zero each time it coincides matches the treg4 treg5 upper 8 bits lower 8 bits upper 8 bits lower 8 bits 000031h 000030h 000033h 000032h treg6 treg7 upper 8 bits lower 8 bits upper 8 bits lower 8 bits 000041h 000040h 000043h 000042h timer register treg5, treg7. the ?lear enable/disable? is set by t4mod and t5mod . if clearing is disabled, the counter operates as a free- running counter. timer registers these two 16-bit registers are used to set the interval time. when the value of up-counter uc4/uc5 matches the set value of this timer register, the comparator match detect signal will be active. setting data for timer register (treg4, treg5, treg6 and treg7) is executed using 2 byte date trans- fer instruction or using 1 byte date transfer instruction twice for lower 8 bits and upper 1 bits in order. treg4 and treg6 timer register is of double buffer structure, which is paired with register buffer. the timer control register t45cr controls whether the double buffer structure should be enabled or disabled. : disabled when = 0, while enabled when = 1. when the double buffer is enabled, the timing to transfer data from the register buffer to the timer register is at the match between the up-counter (uc4/uc5) and timer register treg5/treg7. when reset, it will be initialized to = 0, whereby the double buffer is disabled. to use the double buffer, write data in the timer register, set = 1, and then write the following data in the register buffer. treg4, treg6 and register buffer are allocated to the same memory addresses 000030h/000031h/ 0000400h/000041h. when = 0, same value will be written in both the timer register and register buffer. when = 1, the value is written into only the register buffer. a capture register these 16-bit registers are used to hold the values of the up-counter. data in the capture registers should be read by a 2- byte data load instruction or two 1-byte data load instruc- tion, from the lower 8 bits followed by the upper 8 bits. ? capture input control this circuit controls the timing to latch the value of up-counter uc4/uc5 into (cap1, cap2)/(cap3, cap4). cap 1 cap 2 upper 8 bits lower 8 bits upper 8 bits lower 8 bits 000035h 000034h 000037h 000036h cap 3 cap 4 upper 8 bits lower 8 bits upper 8 bits lower 8 bits 000045h 000044h 000047h 000046h the latch timing of capture register is controlled by regis- ter t4mod /t5mod . when t4mod /t5mod = 00 capture function is disabled. disable is the default on reset.
toshiba corporation 95 TMP96C141AF when t4mod /t5mod = 01 data is loaded to cap1, cap3 at the rise edge of ti4 pin (also used as p80/int4) and ti6 pin (also used as p84/int6) input, while data is loaded to cap2, cap4 at the rise edge of ti5 pin (also used as p81/int5 and ti7 pin (also used as p85/int7) input. (time difference measurement) when t4mod /t5mod = 10 data is loaded to cap1 at the rise edge of ti4 pin input and to cap3 at the rise edge of ti6, while to cap2, cap4 at the fall edge. only in this setting, interrupt int4/int6 occurs at fall edge. (pulse width measurement) when t4mod /t5mod = 11 data is loaded to cap1, cap3 at the rise edge of timer ?p-?p tff1, while to cap2, cap4 at the fall edge. besides, the value of up-counter can be loaded to capture registers by software. whenever ??is written in t4mod , t5mod the current value of up-counter will be loaded to capture register cap1/cap3. it is necessary to keep the prescaler in run mode (trun to be ??. ? comparator these are 16-bit comparators which compare the up-counter uc4/uc5 value with the set value of (treg4, treg5)/(treg6, treg7) to detect the match. when a match is detected, the comparators generate an interrupt (intt4, intt5)/(intt6, intt7) respectively. the up- counter uc4/uc5 is cleared only when uc4/uc5 matches treg5/treg7. (the clearing of up-counter uc4/uc5 can be disabled by setting t4mod / t5mod = 0.) ? timer flip-flop (tff4/tff6) this ?p-?p is inverted by the match detect signal from the comparators and the latch signals to the cap- ture registers. disable/enable of inversion can be set for each element by t4ffcr /t6ffcr . tff4/tff6 will be inverted when ?0?is written in t4ffcr /t6ffcr . also it is set to ??when ?0?is written, and cleared to ??when ?0?is written. the value of tff4/tff6 can be output to the timer output pin to4 (also used as p82) and to6 (also used as p86). ? timer flip-flop (tff5) this ?p-?p is inverted by the match detect signal from the comparator and the latch signal to the capture register cap2. tff5 will be inverted when ?0?is written in t4ffcr /t6ffcr . also it is set to ??when ?0?is written, and cleared to ??when ?0?is written. the value of tff5 can be output to the timer output pin to5 (also used as p82). note: this ?p-?p (tff5) is contained only in the 16-bit timer 4. (1) 16-bit timer mode timer 4 and 5 operate independently. since both timers operate in exactly the same way, timer 4 is used for the purposes of explanation. generating interrupts at ?ed intervals: in this example, the interval time is set in the timer register treg5 to generate the interrupt inttr5. note: x; dont care ? no change 76543210 trun ? ? stop timer 4. intet54 11001000 enable inttr5 and sets interrupt level 4. disables inttr4. t4ffcr 11000011 disable trigger. t4mod 001001** select internal clock for input and disable the capture function. (** = 01, 10, 11) treg5 ******** set the interval timer (16 bits). ******** trun 1x ? start timer 4. (2) 16-bit event counter mode in 16-bit timer mode as described in above, the timer can be used as an event counter by selecting the external clock (ti4/ ti6 pin input) as the input clock. to read the value of the counter, ?st perform ?oftware capture?once and read the captured value. the counter counts at the rise edge of ti4/ti6 pin input. ti4/ti6 pin can also be used as p80/int4 and p84/int6. since both timers operate in exactly the same way, timer 4 is used for the purposes of explanation.
96 toshiba corporation TMP96C141AF note: x; dont care ? no change figure 3.9 (11). programmable pulse generation (ppg) output waveforms 76543210 trun ? ? stop timer 4. treg4 ******** set the duty (16 bits). treg5 ******** set the cycle (16 bits). t45cr 0x x x ? double buffer of treg4 enable. (changes the duty and cycle at the interrupt inttr5) t4ffcr 11001100 set the mode to invert tff4 at the match with treg4/treg5, and also sets tff4 to ?? t4mod 001001** select internal clock for input and disables the capture function. (** = 01, 10, 11) p8cr ? p8fc xxx1xx trun 1x ? start timer 4. note: when used as an event counter, set the prescaler in run mode. 76543210 trun ? ? stop timer 4. p8cr ? set p80 to input mode. intet54 11001000 enable inttr5 and sets interrupt level 4, while disables inttr4. t4ffcr 11000011 disable trigger. t4mod 00100100 select ti4 as the input clock. treg5 ******** set the number of counts (16 bits). trun 1x ? start timer 4. ) assign p82 as to4. (3) 16-bit programmable pulse generation (ppg) output mode since both timers operate in exactly the same way, timer 4 is used for the purposes of explanation. the ppg mode is obtained by inversion of the timer ?p-?p tff4 that is to be enabled by the match of the up-counter uc4 with the timer register treg4 or 5 and to be output to to4 (also used as p82). in this mode, the following conditions must be satis?d. (set value of treg4) < (set value of treg5)
toshiba corporation 97 TMP96C141AF when the double buffer of treg4 is enabled in this mode, the value of register buffer 4 will be shifted in treg4 at match with treg5. this feature makes easy the handling of low duty waves. figure 3.9 (12). operation of register buffer shows the block diagram of this mode. figure 3.9 (13). block diagram of 16-bit ppg mode
98 toshiba corporation TMP96C141AF (4) application examples of capture function the loading of up-counter (uc4) values into the cap- ture registers cap1 and cap2, the timer ?p-?p tff4 inversion due to the match detection by comparators cp4 and cp5, and the output of tff4 status to to4 pin can be enabled or disabled. combined with inter- rupt function, they can be applied in many ways, for example: one-shot pulse output from external trigger pulse frequency measurement a pulse width measurement ? time difference measurement figure 3.9 (14). one-shot pulse output (with delay) one-shot pulse output from external trigger pulse set the up-counter uc4 in free-running mode with the internal input clock, input the external trigger pulse from ti4 pin, and load the value of up-counter into capture register cap1 at the rise edge of the ti4 pin. then set to t4mod = 01. when the interrupt int4 is generated at the rise edge of ti4 input, set the cap1 value (c) plus a delay time (d) to treg4 (= c + d), and set the above set value (c + d) plus a one-shot pulse width (p) to treg5 (= c + d + p). when the interrupt int4 occurs the t4ffcr register should be set that the tff4 inversion is enabled only when the up-counter value matches treg4 or treg5. when interrupt inttr5 occurs, this inversion will be disabled.
toshiba corporation 99 TMP96C141AF setting example: to output 2ms one-shot pulse with 3ms delay to the external trigger pulse to ti4 pin. note: x; dont care ? no change keep counting (free-running). main setting count with f t1. t4mod 101001 load the up-counter value into cap1 at the rise edge of ti4 pin input. t4ffcr 11000010 clear tff4 to zero. disable tff4 inversion. p8cr ? p8fc xxx1xx inte45 1100 enable int4, and disables inttr4 and inttr5. intet54 10001000 trun 1x ? start timer 4. setting of int4 treg4 cap1 + 3ms/ f t1 treg5 treg4 + 2ms/ f t1 t4ffcr 11 enable tff4 inversion when the up-counter value matches treg4 or 5. intet54 1100 enable inttr5. setting of int5 t4ffcr 00 disable tff4 inversion when the up-counter value matches treg 4 or 5. intet54 1000 disable inttr5. ) select p82 as the to4 pin. when delay time is unnecessary, invert timer ?p-?p tff4 when the up-counter value is loaded into capture register 1 (cap1), and set the cap1 value (c) plus the one-shot pulse width (p) to treg5 when the interrupt int4 occurs. the tff4 inversion should be enabled when the up-counter (uc4) value matches treg5, and disabled when generating the interrupt inttr5.
100 toshiba corporation TMP96C141AF figure 3.9 (15). one-shot pulse output (without delay) frequency measurement the frequency of the external clock can be measured in this mode. the clock is input through the ti4 pin, and its frequency is measured by the 8-bit timers (timer 0 and timer 1) and the 16-bit timer/event counter (timer 4). the ti4 pin input should be selected for the input clock of timer 4. the value of the up-counter is loaded figure 3.9 (16). frequency measurement for example, if the value for the level ??width of tff1 of the 8-bit timer is set to 0.5 sec. and the differ- ence between cap1 and cap2 is 100, the frequency will be 100/0.5 [sec.] = 200 [hz]. into the capture register cap1 at the rise edge of the timer ?p-?p tff1 of 8-bit timers (timer 0 and timer 1), and into cap2 at its fall edge. the frequency is calculated by the difference between the loaded values in cap1 and cap2 when the interrupt (intt0 or intt1) is generated by either 8-bit timer.
toshiba corporation 101 TMP96C141AF a pulse width measurement this mode allows measuring the ??level width of an external pulse. while keeping the 16-bit timer/event counter counting (free-running) with the internal clock input, the external pulse is input through the ti4 pin. then the capture function is used to load the uc4 values into cap1 and cap2 at the rising edge and falling edge of the external trigger pulse respectively. the interrupt int4 occurs at the falling edge of ti4. the pulse width is obtained from the difference between the values of cap1 and cap2 and the internal clock cycle. for example, if the internal clock is 0.8 microseconds and the difference between cap1 and cap2 is 100, the pulse width will be 100 x 0.8 = 80 microseconds. figure 3.9 (17). pulse width measurement note: only in this pulse width measuring mode (t4mod = 10), external interrupt int4 occurs at the falling edge of ti4 pin input. in other modes, it occurs at the rising edge. the width of ??level can be measured from the dif- ference between the ?st c2 and the second c1 at the second int4 interrupt. ? time difference measurement this mode is used to measure the difference in time between the rising edges of external pulses input through ti4 and ti5. keep the 16-bit timer/event counter (timer 4) count- ing (free-running) with the internal clock, and load the uc4 value into cap1 at the rising edge of the input pulse to ti4. then the interrupt int4 is generated. similarly, the uc4 value is loaded into cap2 at the rising edge of the input pulse to ti5, generating the inter- rupt int5. the time difference between these pulses can be obtained from the difference between the time counts at which loading the up-counter value into cap1 and cap2 has been done.
102 toshiba corporation TMP96C141AF figure 3.9 (18). time difference measurement (5) different phased pulses output mode in this output mode, signals with any different phase can be outputted by free-running up-counter uc4. when the value in up-counter uc4 and the value in treg4 (treg5) match, the value in tff4 (tff5) is inverted and output to to4 (to5). this mode can only be used by 16-bit timer 4. figure 3.9 (19). phase output cycles (counter over?w time) of the above output waves are listed below. 16mhz 20mhz f t1 1.024msec 0.819msec f t4 4.096msec 3.277msec f t16 16.38 msec 13.11 msec
toshiba corporation 103 TMP96C141AF 3.10 stepping motor control/pattern generation port the TMP96C141AF has two channels (pg0 and pg1) of 4-bit hardware stepping motor control/pattern generation (herein after called pg) which actuate in synchronization with the (8- bit/16-bit) timers. the pg (pg0 and pg1) are shared in 8-bit i/ o ports p6. channel 0 (pg0) is synchronous with 8-bit timer 0 or timer 1, 16-bit timer 5, to update the output. the pg ports are controlled by control registers (pg01cr) and can select either stepping motor control mode or pattern generation mode. each bit of the p6 can be used as the pg port. pg0 and pg1 can be used independently. all pg operate in the same manner except the following points, and thus only the operation of pg0 will be explained below. differences between pg0 and pg1 pg0 pg1 trigger signal from timer 4 from timer 5 figure 3.10 (1). port 6/pg circuit
104 toshiba corporation TMP96C141AF figure 3.10 (2a). pattern generation control register (pg01cr)
toshiba corporation 105 TMP96C141AF figure 3.10 (2b). pattern generation control register (pg01cr)
106 toshiba corporation TMP96C141AF figure 3.10 (3). pattern generation 0 register (pg0reg) figure 3.10 (4). pattern generation 1 register (pg1reg) 76543210 bit symbol pg03 pg02 pg01 pg00 sa03 sa02 sa01 sa00 read/write w r/w after reset 0000 unde?ed function pattern generation 0 (pg0) output latch register (reading the p6 that is set to the pg port allows to read-out.) shift alternate register 0 for the pg mode (4-bit write) register 76543210 bit symbol pg13 pg12 pg11 pg10 sa13 sa12 sa11 sa10 read/write w r/w after reset 0000 unde?ed function pattern generation 1 (pg1) output latch register (reading the p6 that is set to the pg port allows to read-out.) shift alternate register 1 for the pg mode (4-bit write) register pg0reg (004ch) prohibit read modify write pg1reg (004dh) prohibit read modify write
toshiba corporation 107 TMP96C141AF figure 3.10 (5). 16-bit timer trigger control register (t45cr)
108 toshiba corporation TMP96C141AF figure 3.10 (6). connection of timer and pattern generator (1) pattern generation mode pg functions as a pattern generation according to the setting of pg01cr /pat0>. in this mode, writing from cpu is executed only on the shifter alternate register. writing a new data should be done during the interrupt operation of the timer for shift trigger, and a pattern can be output synchronous with the timer. in this mode, set pg01cr and to 1, and pg01cr and to 0. the output of this pattern generator is output to port 6; since port and functions can be switched on a bit basis using port function control register p6fc, any port pin can be assigned to pattern generator output. figure 3.10 (7) shows the block diagram of this mode. example of pattern generation mode
toshiba corporation 109 TMP96C141AF figure 3.10 (7). pattern generation mode block diagram (pg0) - shift due to the shift trigger from timer in this pattern generation mode, only writing the output latch is disabled by hardware, but other functions do the same operation as 1-2 excitation in stepping motor control port mode. accordingly, the data shifted by trigger signal from a timer must be written before the next trigger signal is output.
110 toshiba corporation TMP96C141AF (2) stepping motor control mode 4-phase 1-step/2-step excitation figure 3.10 (8) and figure 3.10 (9) show the output waveforms of 4-phase 1 excitation and 4-phase 2 excita- tion, respectively when channel 0 (pg0) is selected. note: bn indicates the initial value of pg0reg ? b7 b6 b5 b4 x x x x normal rotation reverse rotation figure 3.10 (8). output waveforms of 4-phase 1-step excitation (normal rotation and reverse rotation) - initial value of pg0reg ? 0100 x x x x - initial value of pg0reg ? 0100 x x x x
toshiba corporation 111 TMP96C141AF figure 3.10 (9). output waveforms of 4-phase 2-step excitation (normal rotation) - initial value of pg0reg ? 0100 x x x x the operation when channel 0 is selected is explained below. the output latch of pg0 (also used as p6) is shifted at the rising edge of the trigger signal from the timer to be output to the port. the direction of shift is speci?d by pg01cr : normal rotation (pg00 ? pg01 ? pg02 ? pg03) when is set to ?? reverse rotation (pg00 ? pg01 ? pg02 ? pg03) when ?? four-phase 1-step excitation will be selected when only one bit is set to ??during the initialization of pg, while 4-phase 2-step excitation will be selected when two consecutive bits are set to ?? the value in the shift alternate registers are ignored when the 4-phase 1-step/2-step excitation mode is selected. figure 3.10 (10) shows the block diagram. figure 3.10 (10). block diagram of 4-phase 1-step excitation/2-step excitation (normal rotation)
112 toshiba corporation TMP96C141AF 4-phase 1-2 step excitation figure 3.10 (11) shows the output waveforms of 4- phase 1 -2 step excitation when channel 0 is selected. note: bn denotes the initial value of pg0reg ? b7 b6 b5 b4 b3 b2 b1 b0 normal rotation reverse rotation figure 3.10 (11). output waveforms of 4-phase 1-2 step excitation (normal rotation and reverse rotation) - initial value of pg0reg ? 11001000 - initial value of pg0reg ? 10001100
toshiba corporation 113 TMP96C141AF the initialization for 4-phase 1-2 step excitation is as follows: by rearranging the initial value ?7 b6 b5 b4 b3 b2 b1 b0?to ?7 b3 b6 b2 b5 b1 b4 b0? the consecutive 3 bits are set to ??and other bits are set to ??(positive logic). for example, if b7, b3, and b6 are set to ?", the ini- tial value becomes ?1001000? obtaining the output waveforms as shown in figure 3.10 (11). to get an output waveform of negative logic, set val- ues 1s and 0s of the initial value should be inverted. for example, to change the output waveform shown in fig- ure 3.10 (11) into negative logic, change the initial value to ?0110111? the operation will be explained below for channel 0. the output latch of pg0 (shared by p6) and the shifter alternate register (sa0) for pattern generation are shifted at the rising edge of trigger signal from the timer to be output to the port. the direction of shift is set by pg01cr . figure 3.10 (12) shows the block diagram. figure 3.10 (12). block diagram of 4-phase 1-2 step excitation (normal rotation)
114 toshiba corporation TMP96C141AF setting example: to drive channel 0 (pg0) by 4-phase 1-2 step excitation (normal rotation) when timer 0 is selected, set each register as follows: note: x; dont care ? no change 76543210 trun ? ? ? stop timer 0, and clears it to zero. tmod ? 0 0 x x 0 1 set 8-bit timer mode and selects f t1 as the input clock of timer 0. tffcr ? xxx01010 clear tff1 to zero and enables the inversion trigger by timer 0. treg0 ? ******** set the cycle in timer register. p6cr ? 1111 set p60 ~ p63 bits to the output mode. p6fc ? 1111 set p60 ~ p63 bits to the pg output. pg01cr ? 0011 select pg0 4-phase 1 - 2 step excitation mode and normal rotation. pg0reg ? 11001000 set an initial value. trun ? 11 start timer 0. note: to shift pg, tffcr must be set to ??to enable tff1 inversion. table 3.10 (1) select of trigger signal tff1 inversion pg shift 8-bit timer mode selected by tffcr when the up-counter value matches treg0 or treg1 value. 16-bit timer mode when the up-counter value matches with both treg0 and treg1 values. (the value of up-counter = treg1*2 8 + treg0) ppg output mode when the up-counter value matches with both treg0 and treg1. when the up-counter value matches treg1 value (ppg cycle). pwm output mode when the up-counter value matches treg0 value and pwm cycle. trigger signal for pg is not generated. (3) trigger signal from timer the trigger signal from the timer which is used by pg is not channel 1 of pg can be synchronized with the 16-bit timer timer 4/timer 5. in this case, the pg shift trigger signal from the 16-bit timer is output only when the up-counter uc4/ uc5 value matches treg5/treg7. when using a trigger signal from timer 4, set either t4ffcr or t4mod to ??and a trigger is generated when the value in uc4 and the value in treg5 match. when using a trigger signal from timer 5, set t5ffcr to 1. generates a trigger when the value in uc5 and the value in treg7 match. equal to the trigger signal of timer ?p-?p (tff1, tff4, tff5, and tff6) and differs as shown in table 3.10 (1) depending on the operation mode of the timer.
toshiba corporation 115 TMP96C141AF figure 3.10 (13). output waveforms of 4-phase 1-step excitation setting example: note: x; dont care ? no change 76543210 trun ? 00 stop timer 0, and clears it to zero. tmod ? 10xxxx01 set timer 0 and timer 1 in ppg output mode and selects f t1 as the input clock. tffcr ? xxx0011x enable tff1 inversion and sets tff1 to ?? treg0 ? ******** set the duty of to1 to treg0. treg1 ? ******** set the cycle of to1 to treg1. p7cr ? xxxx1 p7fc ? xxxx1x p6cr ? 1111 p6fc ? 1111 pg01cr ? 0001 set pg0 in 4-phase 1-step excitation mode. pg0reg ? ******** set an initial value. trun ? 1x 11 start timer 0 and timer 1. (4) application of pg and timer output as explained in ?rigger signal from timer? the timing to shift pg and invert tff differs depending on the mode of timer. an application to operate pg while operating an 8-bit timer in ppg mode will be explained below. to drive a stepping motor, in addition to the value of each phase (pg output), synchronizing signal is often required at the timing when excitation is changed over. in this application, port 6 is used as a stepping motor control port to output a synchro- nizing signal to the to1 pin (shared by p71). ) assign p71 as to1. ) assign p60 - 63 as pg0.
116 toshiba corporation TMP96C141AF 3.11 serial channel the TMP96C141AF contains two serial i/o channels for full duplex asynchronous transmission (uart) as well as for i/o extension. the serial channel has the following operation modes: l i/o interface mode mode 0: to transmit and receive i/o data as well as (channel 1 only) the synchronizing signal sclk for extending i/o. mode 1: 7-bit data l asynchronous transmission mode 2: 8-bit data (uart) mode (channel 0 and 1) mode 3: 9-bit data note: TMP96C141AF/tmp96c041af/ tmp96cm40f/tmp96pm40f with channel 0 and 1. in mode 1 and mode 2, a parity bit can be added. mode 3 has wake-up function for making the master controller start slave controllers in serial link (multi-controller system). figure 3.11 (1) shows the data format (for one frame) in each mode. when bit 8 = 1, address (select code) is denoted. when bit 8 = 0, data is denoted. figure 3.11 (1). data formats
toshiba corporation 117 TMP96C141AF the serial channel has a buffer register for transmitting and receiving operations, in order to temporarily store trans- mitted or received data, so that transmitting and receiving operations can be done independently (full duplex). however, in i/o interface mode, sclk (serial clock) pin is used for both transmission and receiving, the channel becomes half-duplex. the receiving data register is of a double buffer structure to prevent the occurrence of overrun error and provides one frame of margin before cpu reads the received data. the receiving data register stores the already received data while the buffer register receives the next frame data. by using cts and rts (there is no rts pin, so any one port must be controlled by software), it is possible to halt data send until cpu ?ishes reading receive data every time a frame is received (handshake function). in the uart mode, a check function is added not to start the receiving operation by error start bits due to noise. the channel starts receiving data only when the start bit is detected to be normal at least twice in three samplings. when the transmission buffer becomes empty and requests the cpu to send the next transmission data, or when data is stored in the receiving data register and the cpu is requested to read the data, inttx or intrx interrupt occurs. besides, if an overrun error, parity error, or framing error occurs during receiving operation, ?g sc0cr/sc1cr will be set. the serial channel 0/1 includes a special baud rate gen- erator, which can set any baud rate by dividing the frequency of four clocks ( f t0, f t2, f t8, and f t32) from the internal pres- caler (shared by 8-bit/16-bit timer) by the value 2 to 16. in i/o interface mode, it is possible to input synchronous signals as well as to transmit or receive data by external clock. 3.11.1 control registers the serial channel is controlled by three control registers sc0cr, sc0mod, and br0cr. transmitted and received data is stored in register sc0buf.
118 toshiba corporation TMP96C141AF note: there is sc1mod (56h) in channel 1 figure 3.11 (2). serial mode control register (channel 0, sc0mod)
toshiba corporation 119 TMP96C141AF note: serial control register for channel 1 is sc1cr (55h). as all error ?gs are cleared after reading, do not test only a single bit with a bit-testing instruction. figure 3.11 (3). serial control register (channel, sc0cr)
120 toshiba corporation TMP96C141AF note: as all error ?gs are cleared after reading, do not test only a single bit with a bit-testing instruction. figure 3.11 (4). serial channel control (channel 0, br0cr) figure 3.11 (5). serial transmission/receiving buffer registers (channel 0, sc0buf) 76543210 tb7 tb6 tb5 tb4 tb3 tb2 tb1 tb0 76543210 rb7 rb6 rb5 rb4 rb3 rb2 rb1 rb0 (transmission) (receiving) sc0buf (50h)
toshiba corporation 121 TMP96C141AF figure 3.11 (6). serial mode control register (channel 1, sc1mod)
122 toshiba corporation TMP96C141AF note: as all error ?gs are cleared after reading, do not test only a single bit with a bit-testing instruction. figure 3.11 (7). serial control register (channel 1, sc1cr)
toshiba corporation 123 TMP96C141AF note: to use baud rate generator, set trun to ?", putting the prescaler in run mode. figure 3.11 (8). baud rate generator control register (channel 0, br0cr) figure 3.11 (9). serial transmission/receiving buffer registers (channel 1, sc1buf) 76543210 tb7 tb6 tb5 tb4 tb3 tb2 tb1 tb0 76543210 rb7 rb6 rb5 rb4 rb3 rb2 rb1 rb0 (transmission) (receiving) sc1buf (0054h)
124 toshiba corporation TMP96C141AF figure 3.11 (10). port 9 function register (p9fc) port 3.11 (11). port 9 open drain enable register (ode)
toshiba corporation 125 TMP96C141AF 3.11.2 con?uration figure 3.11 (12) shows the block diagram of the serial channel 0. figure 3.11 (12). block diagram of the serial channel 0
126 toshiba corporation TMP96C141AF figure 3.11 (13) shows the block diagram of the serial channel 1. figure 3.11 (13). block diagram of the serial channel 1
toshiba corporation 127 TMP96C141AF l uart mode transfer rate = input clock of baud rate generator fr equency divisor of baud rate generator l i/o interface mode transfer rate = input clock of baud rate generator fr equency divisor of baud rate generator the relation between the input clock and the source clock (fc) is as follows: f t0 = fc/4 f t2 = fc/16 f t8 = fc/64 f t32 = fc/256 accordingly, when source clock fc is 12.288 mhz, input clock is f t2 (fc/16), and frequency divisor is 5, the transfer rate in uart mode becomes as follows: transfer rate = fc/16 5 = 12.288 x 10 6 /16/5/16 = 9600 (bps) table 3.11 (1) shows an example of the transfer rate in uart mode. also with 8-bit timer 0, the serial channel can get a transfer rate. table 3.11 (2) shows an example of baud rate using timer 0. note: transfer rate in i/o interface mode is 8 times as fast as the values given in the above table. table 3.11 (1) selection of transfer rate (1) (when baud rate generator is used) unit (kbps) fc [mhz] input clock frequency divisor f t0 (fc/4) f t2 (fc/16) f t8 (fc/64) f t32 (fc/256) 9.830400 2 76.800 19.200 4.800 1.200 - 4 38.400 9.600 2.400 0.600 - 8 19.200 4.800 1.200 0.300 - 0 9.600 2.400 0.600 0.150 12.288000 5 38.400 9.600 2.400 0.600 - a 19.200 4.800 1.200 0.300 14.745600 3 76.800 19.200 4.800 1.200 - 6 38.400 9.600 2.400 0.600 - c 19.200 4.800 1.200 0.300 baud rate generator baud rate generator comprises a circuit that gener- ates transmission and receiving clocks to determine the transfer rate of the serial channel. the input clock to the baud rate generator, f t0 (fc/ 4), f t2 (fc/16), f t8 (fc/64), or f t32 (fc/256) is generated by the 9-bit prescaler which is shared by the timers. one of these input clocks is selected by the baud rate genera- tor control register br0cr/br1cr . the baud rate generator includes a 4-bit frequency divider, which divides frequency by 2 to 16 values to determine the transfer rate. how to calculate a transfer rate when the baud rate generator is used is explained below. ? 16 ? 2 ? 16
128 toshiba corporation TMP96C141AF how to calculate the transfer rate (when timer 0 is used): transfer rate = fc treg0 x 8 x 16 (when timer 0 (input clock f t1) is used) input clock of timer 0 f t1 = fc /8 f t4 = fc /32 f t16 = fc /128 note: timer 0 match detect signal cannot be used as the transfer clock in i/o interface mode. table 3.11 (2) selection of transfer rate (1) (when timer 0 (input clock f t1) is used) unit (kbps) fc treg0 12.288mhz 12mhz 9.8304mhz 8mhz 6.144mhz 1h 96 76.8 62.5 48 2h 48 38.4 31.25 24 3h 32 31.25 16 4h 24 19.2 12 5h 19.2 9.6 8h 12 9.6 6 ah 9.6 4.8 10h 6 4.8 3 14h 4.8 2.4 - serial clock generation circuit this circuit generates the basic clock for transmitting and receiving data. 1) i/o interface mode (channel 1 only) when in sclk output mode with the set- ting of sc1cr = ?", the basic clock will be generated by dividing by 2 the output of the baud rate generator as described before. when in sclk input mode with the setting of sc1cr = ?", the rising edge or falling edge will be detected accord- ing to the setting of sc1cr regis- ter to generate the basic clock. 2) asynchronous communication (uart) mode according to the setting of sc0cr and sc1cr , the above baud rate gen- erator clock, internal clock f 1 (500 kbps @ fc = 16 mhz), or the match detect signal from timer 0 will be selected to generate the basic clock sioclk. a receiving counter the receiving counter is a 4-bit binary counter used in asynchronous communication (uart) mode and counts up by sioclk clock. sixteen pulses of sioclk are used for receiving one bit of data, and the data bit is sampled three times at 7th, 8th and 9th clock. with the three samples, the received data is evaluated by the rule of majority. for example, if the sampled data bit is ?", ??and ??at 7th, 8th and 9th clock respectively, the received data is evaluated as ?? the sampled data ?", ??and ??is evaluated that the received data is ?? ? receiving control 1) i/o interface mode (channel 1 only) when in sclk1 output mode with the setting of sc1cr = ?", rxd1 signal will be sampled at the rising edge of shift clock which is output to sclk pin. when in sclk input mode with the set- ting sc1cr = ?", rxd1 signal will be sampled at the rising edge or falling edge of sclk input according to the setting of sc1cr register.
toshiba corporation 129 TMP96C141AF 2) asynchronous communication (uart) mode the receiving control has a circuit for detecting the start bit by the rule of majority. when two or more ??are detected during 3 samples, it is recognized as start bit and the receiving operation is started. data being received is also evaluated by the rule of majority. ? receiving buffer to prevent overrun error, the receiving buffer has a double buffer structure. received data is stored one bit by one bit in the receiving buffer 1 (shift register type). when 7 bits or 8 bits of data are stored in the receiving buffer 1, the stored data is transferred to another receiving buffer 2 (sc0buf/ sc1buf), generating an interrupt intrx0/intrx1. the cpu reads only receiving buffer 2 (sc0buf/sc1buf). even before the cpu reads the receiving buffer 2 (sc0buf/sc1buf), the received data can be stored in the receiving buffer 1. however, unless the receiving buffer 2 (sc0buf/sc1buf) is read before all bits of the next data are received by the receiving buffer 1, an over- run error occurs. if an overrun error occurs, the contents of the receiving buffer 1 will be lost, although the contents of the receiving buffer 2 and sc0cr sc1cr are still preserved. the parity bit added in 8-bit uart mode and the most signi?ant bit (msb) in 9-bit uart mode are stored in sc0cr /sc1cr . when in 9-bit uart mode, the wake-up function of the slave controllers is enabled by setting sc0mod /sc1mod to ?", and interrupt intrx0/ intrx1 occurs only when sc0cr /sc1cr is set to ?? ? transmission counter transmission counter is a 4-bit binary counter which is used in asynchronous communication (uart) mode and, like a receiving counter, counts by sioclk clock, generating txdclk every 16 clock pulses. figure 3.11 (14). generation of transmission clock ? transmission controller 1) i/o interface mode (channel 1 only) in sclk output mode with the setting of sc1cr = ?", the data in the trans- mission buffer are output bit by bit to txd1 pin at the rising edge of shift clock which is output from sclk1 pin. in sclk input mode with the setting sc1cr = ?", the data in the trans- mission buffer are output bit by bit to txd1 pin at the rising edge or falling edge of sclk input according to the setting of sc1cr register. 2) asynchronous communication (uart) mode when transmission data is written in the transmission buffer sent from the cpu, trans- mission starts at the rising edge of the next txdclk, generating a transmission shift clock txdsft.
130 toshiba corporation TMP96C141AF handshake function serial channel 0 has a cts0 pin. using this pin, data can be sent in units of one frame; thus, overrun errors can be avoided. the handshake function is enabled/disabled by sc0mod . when the cts0 pin goes high, after completion of the current data send, data send is halted until the cts0 pin goes low again. the inttx0 interrupts are generated, requests the next send data to the cpu. though there is no r ts pin, a hand- shake function can be easily con?ured by setting any port assigned to the r ts func- tion. the r ts should be output ?igh?to request data send halt after data receive is completed by a software in the rxd interrupt routine. figure 3.11 (15). handshake function note 1: if the cts signal falls during transmission, the next data is not sent after the completion of the current transmission. note 2: transmission starts at the ?st txdclk clock fall after the cts signal falls. figure 3.11 (16). timing of cts (clear to send)
toshiba corporation 131 TMP96C141AF generating timing 1) uart mode note: framing error occurs after an interrupt has occurred. therefore, to check for framing error during interrupt operation, it is necessary to wait for 1 bit period of transfer rate. receiving mode 9-bit 8-bit + parity 8-bit, 7-bit + parity, 7-bit interrupt timing center of last bit (bit 8) center of last bit (parity bit) center of stop bit framing error timing center of stop bit center of stop bit center of stop bit parity error timing center of last bit (bit 8) center of last bit (parity bit) center of stop bit overrun error timing center of last bit (bit 8) center of last bit (parity bit) center of stop bit transmitting mode 9-bit 8-bit + parity 8-bit, 7-bit + parity, 7-bit interrupt timing just before last bit is transmitted. ?? 11 ? transmission buffer transmission buffer (sc0buf/sc1buf) shifts to and sends the transmission data written from the cpu from the least signi?ant bit (lsb) in order, using transmission shift clock txdsft which is generated by the transmis- sion control. when all bits are shifted out, the transmis- sion buffer becomes empty and generates inttx0/ inttx1 interrupt. parity control circuit when serial channel control register sc0cr / sc1cr is set to ?", it is possible to transmit and receive data with parity. however, parity can be added only in 7-bit uart or 8-bit uart mode. with sc0cr /sc1cr register, even (odd) parity can be selected. for transmission, parity is automatically generated according to the data written in the transmission buffer scbuf, and data are transmitted after being stored in sc0buf /sc1buf when in 7-bit uart mode while in scmod /scmod when in 8-bit uart mode. and must be set before transmission data are written in the transmission buffer. for receiving, data is shifted in the receiving buffer 1, and parity is added after the data is transferred in the receiving buffer 2 (sc0buf/sc1buf), and then com- pared with sc0buf /sc1buf when in 7- bit uart mode and with sc0mod /sc1mod when in 8-bit uart mode. if they are not equal, a parity error occurs, and sc0cr /sc1cr ?g is set error flag three error ?gs are provided to increase the reliabil- ity of receiving data. 1. overrun error if all bits of the next data are received in receiving buffer 1 while valid data is stored in receiving buffer 2 (scbuf), an overrun error will occur. 2. parity error the parity generated for the data shifted in receiving buffer 2 (scbuf) is compared with the parity bit received from rxd pin. if they are not equal, a parity error occurs. 3. framing error the stop bit of received data is sampled three times around the center. if the majority is ?", a framing error occurs.
132 toshiba corporation TMP96C141AF 2) i/o interface mode transmission interrupt timing sclk output mode immediately after rise of last sclk signal (see figure 3.11 (19) ). sclk input mode immediately after rise of last sclk signal (rising mode), or immediately after fall in falling mode (see figure 3.11 (20)). receiving interrupt timing sclk output mode timing used to transfer received data to data receive buffer 2 (sc1buf); that is, immediately after last sclk (see figure 3.11 (21)). sclk input mode timing used to transfer received data to data receive buffer 2 (sc1buf); that is, immediately after sclk (see figure 3.11 (22)). 3.11.3 operational description (1) mode 0 (i/o interface mode) this mode is used to increase the number of i/o pins for trans- mitting or receiving data to or from the external shifter register. this mode includes sclk output mode to output syn- chronous clock sclk and sclk input mode to input external synchronous clock sclk. figure 3.11 (17). example of sclk output mode connection figure 3.11 (18). example of sclk input mode connection
toshiba corporation 133 TMP96C141AF transmission in sclk output mode, 8-bit data and synchronous clock are output from txd pin and sclk pin, respectively, each time the cpu writes data in the transmission buffer. when all data is output, intes1 will be set to generate inttx1 interrupt. figure 3.11 (20). transmitting operation in i/o interface mode (sclk input mode) figure 3.11 (19) transmitting operation in i/o interface mode (sclk output mode) when all data are output, intes1 will be set to generate inttx1 interrupt. in sclk output mode, 8-bit data are output from txd1 pin when sclk input becomes active while data are written in the transmission buffer by cpu.
134 toshiba corporation TMP96C141AF receiving in sclk output mode, synchronous clock is output from sclk pin and the data is shifted in the receiving buffer 1 whenever the receive interrupt ?g intes1 is cleared by reading the received data. when 8-bit data are received, the data will be trans- ferred in the receiving buffer 2 (sc1buf) at the timing shown below, and intes1 will be set again to generate intrx1 interrupt. figure 3.11 (21). receiving operation in i/o interface mode (sclk output mode) in sclk input mode, the data is shifted in the receiving buffer 1 when sclk input becomes active, while the receive interrupt ?g intes1 is cleared by read- ing the received data. when 8-bit data is received, the data will be shifted in the receiving buffer 2 (sc1buf) at the timing shown below, and intes1 will be set again to generate intrx interrupt. figure 3.11 (22). receiving operation in i/o interface mode (sclk input mode) note: for data receiving, the system must be placed in the receive enable state (scmod = ??
toshiba corporation 135 TMP96C141AF note: x; dont care ? no change 76543210 p9cr ? x x ? p9fc ? xxxxx1 sc0mod ? x0x0101 set 7-bit uart mode. sc0cr ? x11xxx00 add an even parity. br0cr ? 0x100101 set transfer rate at 2400 bps. trun ? 1x start the prescaler for the baud rate generator. intes0 ? 1100 enable inttx0 interrupt and sets interrupt level 4. sc0buf ? ******** set data for transmission. direction of transmission (transmission rate: 2400 bps @ fc = 12.288mhz) (2) mode 1 (7-bit uart mode) the 7-bit mode can be set by setting serial channel mode register sc0mod /sc1mod to ?1? in this mode, a parity bit can be added, and the addi- tion of a parity bit can be enabled or disabled by serial channel control register sc0cr /sc1cr , and even parity or odd parity is selected by sc0cr /sc1cr when is set to ?? (enable). setting example: when transmitting data with the following format, the control registers should be set as described below. channel 0 is explained here. ) select p90 as the txd pin. (3) mode 2 (8-bit uart mode) the 8-bit uart mode can be speci?d by setting sc0mod / sc1mod to ?0? in this mode, parity bit can be added, the addition of a parity bit is enabled or disabled by sc0cr / direction of transmission (transmission rate: 9600 bps @ fc = 12.288mhz) sc1cr , and even parity or odd parity is selected by sc0cr /sc1cr when is set to ??(enable). setting example: when receiving data with the following format, the control register should be set as described below.
136 toshiba corporation TMP96C141AF note: x; dont care ? no change main setting 76543210 p9cr ? x x 0 select p91 (rxd) as the input pin. sc0mod ? 01x1001 enable receiving in 8-bit uart mode. sc0cr ? x01xxx00 add an odd parity. br0cr ? 0x010101 set transfer rate at 9600 bps. trun ? 1x start the prescaler for the baud rate generator. intes0 ? 1100 enable inttx0 interrupt and sets interrupt level 4. interrupt processing acc ? sc0cr and 00011100 if acc 1 0 then error acc ? sc0buf read the received data. ) check for error. (4) mode 3 (9-bit uart mode) the 9-bit uart mode can be speci?d by setting sc0mod /sc1mod to ?1? in this mode, parity bit cannot be added for transmission, the msb (9th bit) is written in scm0d , while in receiving it is stored in sccr . for writing and reading the buffer, the msb is read or written ?st, then sc0buf/sc1buf. w ake-up function in 9-bit uart mode, the wake-up function of slave controllers is enabled by setting sc0mod / sc1mod to ?? the interrupt intrx1/intrx0 occurs only when = 1 . note: txd pin of the slave controllers must be in open drain output mode. figure 3.11 (23). serial link using wake-up function
toshiba corporation 137 TMP96C141AF protocol select the 9-bit uart mode for master and slave controllers. set sc0mod /sc1mod bit of each slave controller to ??to enable data receiving. the master controller transmits one-frame data including the 8-bit select code for the slave control- lers. the msb (bit 8) is set to ?? each slave controller receives the above frame, and clears wu bit to ??if the above select code matches its own select code. the master controller transmits data to the specified slave controller whose sc0mod /sc1mod bit is cleared to ?.?the msb (bit 8) is cleared to ?? the other slave controllers (with the bit remain- ing at ?? ignore the receiving data because their msbs (bit 8 or ) are set to ??to disable the interrupt intrx0/intrx1. the slave controllers (wu = 0) can transmit data to the master controller, and it is possible to indicate the end of data receiving to the master controller by this transmission.
138 toshiba corporation TMP96C141AF setting example: to link two slave controllers serially with the master controller, and use the internal clock f 1 (fc/2) as the transfer clock. since serial channels 0 and 1 operate in exactly the same way, channel 0 is used for the purposes of explanation. setting the master controller setting the slave controller 2 main setting p9cr ? x x 01 p9fc ? xxxxx1 intes0 ? 11001101 enable inttx0 and sets the interrupt level 4. enable intrx0 and sets the interrupt level 5. sc0mod ? 10101110 set f 1 (fc/2) as the transmission clock in 9-bit uart mode. sc0buf ? 00000001 set the select code for slave controller 1. inttx0 interrupt sc0mod ? ? set tb8 to ?? sc0buf ? ******** set data for transmission. main setting p9cr ? x x 01 p9fc ? xxxxx1 ode ? xxxxxx1 intes0 ? 11011110 enable intrx0 and inttx0. sc0mod ? 00111110 set to ??in the 9-bit uart transmission mode with transfer clock f 1 (fc/2). intrx0 interrupt acc ? sc0buf if acc = select code then sc0mod4 ? ? clear to ?? ) select p90 as txd pin and p91 as rxd pin. ) select p91 as rxd pin and p90 as txd pin (open drain output).
toshiba corporation 139 TMP96C141AF 3.12 analog/digital converter the TMP96C141AF contains a high-speed analog/digital con- verter (a/d converter) with 4- channel analog input that features 10-bit successive approximation. figure 3.12 (1) shows the block diagram of the a/d con- verter. the 4-channel analog input pins (an3 to an0) are shared by input-only p5 and so can be used as input port. figure 3.12 (1). block diagram of a/d converter note: this a/d converter does not have a built-in sample and hold circuit. therefore, when a/d converting high-frequency signals, connect a sample and hold circuit externally.
140 toshiba corporation TMP96C141AF figure 3.12 (2). a/d control register
toshiba corporation 141 TMP96C141AF figure 3.12 (3-1). a/d conversion result register (adreg0, 1) 76543210 bit symbol adr01 adr00 read/write r after reset unde?ed 111111 function lower 2 bits of a/d result for an0 are stored. 76543210 bit symbol adr09 adr08 adr07 adr06 adr05 adr04 adr03 adr02 read/write r after reset unde?ed function upper 8 bits of a/d result for an0 are stored. 76543210 bit symbol adr11 adr10 read/write r after reset unde?ed 111111 function lower 2 bits of a/d result for an1 are stored. 76543210 bit symbol adr19 adr18 adr17 adr16 adr15 adr14 adr13 adr12 read/write r after reset unde?ed function upper 8 bits of a/d result for an1 are stored. adreg0l (0060h) adreg0h (0061h) adreg1l (0062h) adreg1h (0063h)
142 toshiba corporation TMP96C141AF figure 3.12 (3-2). a/d conversion result register (adreg2, 3) 76543210 bit symbol adr21 adr20 read/write r after reset unde?ed 111111 function lower 2 bits of a/d result for an2 are stored. 76543210 bit symbol adr29 adr28 adr27 adr26 adr25 adr24 adr23 adr22 read/write r after reset unde?ed function upper 8 bits of a/d result for an2 are stored. 76543210 bit symbol adr31 adr30 read/write r after reset unde?ed 111111 function lower 2 bits of a/d result for an3 are stored. 76543210 bit symbol adr39 adr38 adr37 adr36 adr35 adr34 adr33 adr32 read/write r after reset unde?ed function upper 8 bits of a/d result for an3 are stored. adreg2l (0064h) adreg2h (0065h) adreg3l (0066h) adreg3h (0067h)
toshiba corporation 143 TMP96C141AF 3.12.1 operation (1) analog reference voltage high analog reference voltage is applied to the vref pin, and low analog reference voltage is applied to agnd pin. the reference voltage between vreg and agnd is divided by 1024 using ladder resistance, and com- pared with the analog input voltage for a/d conversion. (2) analog input channels analog input channel is selected by admod . however, which channel to select depends on the operation mode of the a/d converter. in ?ed analog input mode, one channel is selected by admod among four pins: an0 to an3. in analog input channel scan mode, the number of channels to be scanned from an0 is speci?d by admod , such as an0 an1, an0 an1 an2, and an0 an1 an2 an3. when reset, a/d conversion channel register will be ini- tialized to admod = 00, so that an0 pin will be selected. the pins which are not used as analog input channel can be used as ordinary input port p5. (3) starting a/d conversion a/d conversion starts when a/d conversion register admod is written ?". when a/d conversion starts, a/d conversion busy ?g admod which indicates ?/d conversion is in progress?will be set to ?". (4) a/d conversion mode both ?ed a/d conversion channel mode and a/d conversion channel scan mode have two conversion modes, i.e., single and repeat conversion modes. in ?ed channel repeat mode, conversion of speci?d one channel is executed repeatedly. in scan repeat mode, scanning from an0, an3 is executed repeatedly. a/d conversion mode is selected by admod . (5) a/d conversion speed selection there are two a/d conversion speed modes: high speed mode and low speed mode. the selection is executed by admod register. when reset, admod will be initialized to ?,? so that high speed conversion mode will be selected. (6) a/d conversion end and interrupt a/d conversion single mode admod for a/d conversion end will be set to ?,?admod ?g will be reset to ?,? and intad interrupt will be enabled when a/d conver- sion of speci?d channel ends in ?ed conversion channel mode or when a/d conversion of the last channel ends in channel scan mode. a/d conversion repeat mode for both ?ed conversion channel mode and con- version channel scan mode, intad should be disabled when in repeat mode. always set the inte0ad at ?00,?that disables the interrupt request. write ??to admod to end the repeat mode. then, the repeat mode will be exited as soon as the conversion in progress is completed. (7) storing the a/d conversion result the results of a/d conversion are stored in adreg0 to adreg3 registers for each channel. in repeat mode, the registers are updated whenever conversion ends. adreg0 to adreg3 are read-only registers. (8) reading the a/d conversion result the results of a/d conversion are stored in adreg0 to adreg3 registers. when the contents of one of adreg0 to adreg3 registers are read, admod will be cleared to ?". setting example: when the analog input voltage of the an3 pin is a/d converted and the result is stored in the memory address ff10h by a/d interrupt intad routine.
144 toshiba corporation TMP96C141AF note: x; dont care ? no change main setting inte0ad 1100 enable intad and sets interrupt level 4. admod xx000111 specify an3 pin as an analog input channel and starts a/d conversion in high speed mode. intad routine wa adreg3 read adreg3l and adreg3h values and writes to wa (16 bit). wa > > 6 right-shifts wa six times and writes 0 in upper bits. (00ff10h) wa writes contents of wa in memory at ff10h. when the analog input voltage of an0 ~ an2 pins is a/d converted in high speed conversion channel scan repeat mode. inte0ad 100 disable intad. admod xx110110 start the a/d conversion of analog input channels an0 ~ an2 in the high-speed scan repeat mode. 3.13 watchdog timer (runaway detecting timer) the TMP96C141AF is containing watchdog timer of runaway detecting. the watchdog timer (wdt) is used to return the cpu to the normal state when it detects that the cpu has started to malfunction (runaway) due to causes such as noise. when the watchdog timer detects a malfunction, it generates a non- maskable interrupt to notify the cpu of the malfunction, and outputs 0 externally from watchdog timer out pin wdtout to notify the peripheral devices of the malfunction. connecting the watchdog timer output to the reset pin internally forces a reset.
toshiba corporation 145 TMP96C141AF 3.13.1 con?uration figure 3.13 (1) shows the block diagram of the watchdog timer (wdt). figure 3.13 (1). block diagram of watchdog timer
146 toshiba corporation TMP96C141AF the watchdog timer is a 22-stage binary counter which uses f (fc/2) as the input clock. there are four outputs from the binary counter: 2 16 /fc, 2 18 /fc, 2 20 /fc, and 2 22 /fc. selecting one of the outputs with the wdmod register generates a watch- dog interrupt, and outputs watchdog timer out when an over- ?w occurs. since the watchdog timer out pin (wdtout ) outputs ?? due to a watchdog timer over?w, the peripheral devices can figure 3.13 (2). normal mode figure 3.13 (3). reset mode be reset. the watchdog timer out pin is set to 1 by clearing the watchdog timer (by writing a clear code 4eh in the wdcr reg- ister). in other words, the wdtout keeps outputting ??until the clear code is written. the watchdog timer out pin can also be connected to the reset pin internally. in this case, the watchdog timer out pin (wdtout ) outputs 0 at 8 to 20 states (800ns to 2 m s @ 20mhz) and resets itself.
toshiba corporation 147 TMP96C141AF 3.13.2 control registers watchdog timer wdt is controlled by two control registers wdmod and wdcr. (1) watchdog timer mode register (wdmod) setting the detecting time of watchdog timer this 2-bit register is used to set the watchdog timer interrupt time for detecting the runaway. this register is initialized to wdmod = 00 when reset, and therefore 2 16 /fc is set. (the number of states is approximately 32,768). watchdog timer enable/disable control register when reset, wdmod is initialized to ?? enable the watchdog timer. to disable, it is necessary to clear this bit to ??and write the disable code (b1h) in the watchdog timer control register wdcr. this makes it dif?ult for the watchdog timer to be disabled by runaway. however, it is possible to return from the disable state to enable state by merely setting to ?". a watchdog timer out reset connection this register is used to connect the output of the watchdog timer with reset terminal, internally. since wdmod is initialized to 0 at reset, a reset by the watchdog timer will not be performed. (2) watchdog timer control register (wdcr) this register is used to disable and clear the binary counter of the watchdog timer function. disable control wdmod 0? x clear wdmod to ?". wdcr 10110001 write the disable code (b1h). enable control set wdmod to ?". watchdog timer clear control the binary counter can be cleared and resume counting by writing clear code (4eh) into the wdcr reg- ister. wdcr 01001110 write the clear code (4eh).
148 toshiba corporation TMP96C141AF figure 3.13 (4). watchdog timer mode register
toshiba corporation 149 TMP96C141AF figure 3.13 (5). watchdog timer control register
150 toshiba corporation TMP96C141AF 3.13.3 operation the watchdog timer generates interrupt intwd after the detecting time set in the wdmod register and outputs a low level signal. the watchdog timer must be zero- cleared by software before an intwd interrupt is generated. if the cpu malfunctions (runaway) due to causes such as noise, but does not execute the instruction used to clear the binary counter, the binary counter over?ws and an intwd interrupt is generated. the cpu detects malfunction (runaway) due to the intwd interrupt and it is possible to return to normal oper- ation by an anti-malfunction program. by connecting the watchdog timer out pin to peripheral devices?resets, a cpu malfunction can also be acknowledged to other devices. the watchdog timer restarts operation immediately after resetting is released. the watchdog timer stops its operation in the idle and stop modes. in the run mode, the watchdog timer is enabled. however, the function can be disabled when entering the run mode. example: clear the binary counter set the watchdog timer detecting time to 2 18 /fc a disable the watchdog timer ? set idle mode ? set the stop mode (warming up time: 2 16 /fc) wdcr 01001110 write clear code (4eh). wdmod 101? x wdmod 0? x clear wdte to ?". wdcr 10110001 write disable code (b1h). wdmod 0 1 0 x x disables wdt and sets idle mode. wdcr 10110001 executes halt command set the standby mode wdmod 101xx set the stop mode. executes halt command execute halt instruction. set the standby mode.
toshiba corporation 151 TMP96C141AF 4. electrical characteristics note: i-dar is guaranteed for a total of up to 8 ports. 4.1 absolute maximum (TMP96C141AF) symbol parameter rating unit v cc power supply voltage -0.5 ~ 6.5 v v in input voltage -0.5 ~ v cc + 0.5 v s iol output current (total) 100 ma s ioh output current (total) -100 ma pd power dissipation (ta = 70 c) 600 mw t solder soldering temperature (10s) 260 c t stg storage temperature -65 ~ 150 c t opr operating temperature -20 ~ 70 c 4.2 dc characteristics (TMP96C141AF) v cc = 5v 10%, ta = -20 ~ 70 c (typical values are for ta = 25 c and v cc = 5v) symbol parameter min max unit test condition v il input low voltage (ad0-15) -0.3 0.8 v v il1 p2, p3, p4, p5, p6, p7, p8, p9 -0.3 0.3v cc v v il2 reset , nmi , into (p87) -0.3 0.25v cc v v il3 ea -0.3 0.3 v v il4 x1 -0.3 0.2v cc v v ih input high voltage (ad0-15) 2.2 v cc + 0.3 v v ih1 p2, p3, p4, p5, p6, p7, p8, p9 0.7v cc v cc + 0.3 v v ih2 reset , nmi , into (p87) 0.75v cc v cc + 0.3 v v ih3 ea v cc - 0.3 v cc + 0.3 v v ih4 x1 0.8v cc v cc + 0.3 v v ol output low voltage 0.45 v i ol = 1.6ma v oh output high voltage 2.4 v i oh = -400 m a v oh1 0.75v cc v i oh = -100 m a v oh2 0.9v cc v i oh = - 20 m a i dar darlington drive current (8 output pins max.) -1.0 -3.5 ma v ext - 1.5v r ext = 1.1k w i li input leakage current 0.02 (typ) 5 m a 0.0 v in v cc i lo output leakage current 0.05 (typ) 10 m a 0.2 v in v cc - 0.2 i cc operating current (run) idle stop (ta = -20 ~ 70 c) stop (ta = 0 ~ 50 c) 26 (typ) 1.7 (typ) 0.2 (typ) 50 10 50 10 ma ma m a m a t osc = 16mhz 0.2 v in v cc - 0.2 0.2 v in v cc - 0.2 v stop power down voltage (@stop, ram back up) 2.0 6.0 v v il2 = 0.2v cc , v ih2 = 0.8v cc r rst reset pull up register 50 150 k w c io pin capacitance 10 pf tosc = 1mhz v th schmitt width reset , nmi , into (p87) 0.4 1.0 (typ) v r k pull down/up register 50 150 k w
152 toshiba corporation TMP96C141AF ac measuring conditions output level: high 2.2v /low 0.8v, cl50pf (however cl = 100pf for ad0 ~ ad15, ad0 ~ ad23, ale, rd , wr , hwr , r/w , clk, ras , cas0 ~ cas2 ) input level: high 2.4v /low 0.45v (ad0 ~ ad15) high 0.8vcc /low 0.2vcc (except for ad0 ~ ad15) 4.3 ac electrical characteristics (TMP96C141AF) v cc = 5v 10%, ta = -20 ~ 70 c (4mhz ~ 20mhz) no. symbol parameter variable 16mhz 20mhz unit min max min max min max 1t osc osc. period (= x) 50 250 62.5 50 ns 2t clk clk width 2x - 40 85 60 .0 ns 3t ak a0 - 23 valid clk hold 0.5x - 20 11 .0 5 0 ns 4t ka clk valid a0 - 23 hold 1.5x - 70 24 0 5 0 ns 5t al a0-15 valid ale fall 0.5x - 15 16 0 10 0 ns 6t la ale fall a0 - 15 hold 0.5x - 15 16 0 10 0 ns 7t ll ale high width x - 40 23 .0 10 0 ns 8t lc ale fall rd /wr fall 0.5x - 30 1 .0 -5 ns 9t cl rd /wr rise ale rise 0.5x - 20 11 .0 5 0 ns 10 t acl a0 - 15 valid rd /wr fall x - 25 38 .0 25 0 ns 11 t ach a0 - 23 valid rd /wr fall 1.5x - 50 44 .0 25 .0 ns 12 t ca rd /wr rise a0 - 23 hold 0.5x - 20 11 .0 5ns 13 t adl a0 - 15 valid d0 - 15 input 3.0x - 45 143 105 ns 14 t adh a0 - 23 valid d0 - 15 input 3.5x - 65 154 110 ns 15 t rd rd fall d0 - 15 input 2.0x - 50 75 50 ns 16 t rr rd low width 2.0x - 40 85 .0 60 .0 ns 17 t hr rd rise d0 - 15 hold 0 0 .0 0 .0 ns 18 t rae rd rise a0 - 15 output x - 15 48 .0 35 .0 ns 19 t ww wr low width 2.0x - 40 85 .0 60 .0 ns 20 t dw d0 - 15 valid wr rise 2.0x - 50 75 .0 50 .0 ns 21 t wd wr rise d0 - 15 hold 0.5x - 10 21 .0 15 .0 ns 22 t aeh a0 - 23 valid w ait input (1wait + n mode) 3.5x - 90 129 85 ns 23 t awl a0 - 15 valid w ait input (1wait + n mode) 3.0x - 80 108 70 ns 24 t cw rd /wr fall w ait hold (1wait + n mode) 2.0x + 0 125 .0 100 .0 ns 25 t aph a0 - 23 valid port input 2.5x - 120 80 36 ns 26 t aph2 a0 - 23 valid port hold 2.5x + 50 206 .0 175 .0 ns 27 t cp wr rise port valid 200 200 200 ns 28 t asrh a0 - 23 valid ras fall 1.0x - 40 23 .0 10 .0 ns 29 t asrl a0 - 15 valid ras fall 0.5x - 15 16 .0 10 .0 ns 30 t rac ras fall d0 - 15 input 2.5x - 70 130 86 ns 31 t rah ras fall a0 - 15 hold 0.5x - 15 16 .0 10 .0 ns 32 t ras ras low width 2.0x - 40 85 .0 60 .0 ns 33 t rp ras high width 2.0x - 40 85 .0 60 .0 ns 34 t rsh cas fall ras rise 1.0x - 35 28 .0 15 .0 ns 35 t rsc ras rise cas rise 0.5x - 25 6 .0 0 .0 ns 36 t rcd ras fall cas fall 1.0x - 40 23 .0 10 0 ns 37 t cac cas fall d0 - 15 input 1.5x - 65 29 10 ns 38 t cas cas low width 1.5x - 30 64 .0 40 .0 ns
toshiba corporation 153 TMP96C141AF (1) read cycle
154 toshiba corporation TMP96C141AF (2) write cycle
toshiba corporation 155 TMP96C141AF 4.4 a/d conversion characteristics (TMP96C141AF) v cc = 5v 10% ta = -20 ~ 70 c symbol parameter min typ max unit v ref analog reference voltage v cc - 1.5 v cc v cc v a gnd analog reference voltage v ss v ss v ss v ain analog input voltage range v ss v cc i ref analog current for analog reference voltage 0.5 1.5 ma error (quantize error of 0.5 lsb not included) 4 fc 16mhz low speed conversion mode 1.5 (tbd) 4.0 lsb high speed conversion mode 3.0 (tbd) 6.0 16 fc 20mhz low speed conversion mode 1.5 (tbd) 4.0 high speed conversion mode 4.0 (tbd) 8.0 4.5 serial channel timing - i/o interface mode v cc = 5v 10% ta = -20 ~ 70 c (1) sclk input mode symbol parameter variable 16mhz 20mhz unit min max min max min max t scy sclk cycle 16x 1 0.8 m s t oss output data rising edge of sclk t scy /2 - 5x - 50 137 100 ns t ohs sclk rising edge output data hold 5x - 100 212 150 ns t hsr sclk rising edge input data hold 0 0 0 ns t srd sclk rising edge effective data input t scy - 5x - 100 587 450 ns (2) sclk output mode symbol parameter variable 16mhz 20mhz unit min max min max min max t scy sclk cycle (programmable) 16x 8192x 1 512 0.8 409.6 m s t oss output data rising edge of sclk t scy - 2x - 150 725 550 ns t ohs sclk rising edge output data hold 2x - 80 45 20 ns t hsr sclk rising edge input data hold 0 0 0 ns t srd sclk rising edge effective data input t scy - 2x - 150 725 550 ns 4.6 timer/counter input clock (ti0, ti4, ti5, ti6, ti7) v cc = 5v 10% ta = -20 ~ 70 c symbol parameter variable 16mhz 20mhz unit min max min max min max t vck clock cycle 8x + 100 600 500 ns t vckl low level clock pulse width 4x + 40 290 240 ns t vckh high level clock pulse width 4x + 40 290 240 ns
156 toshiba corporation TMP96C141AF 4.7 interrupt operation v cc = 5v 10% ta = -20 ~ 70 c symbol parameter variable 16mhz 20mhz unit min max min max min max t intal nmi , int0 low level pulse width 4x 250 200 ns t intah nmi , int0 high level pulse width 4x 250 200 ns t intbl int4 ~ int7 low level pulse width 8x + 100 600 500 ns t intbh int4 ~ int7 high level pulse width 8x + 100 600 500 ns
toshiba corporation 157 TMP96C141AF 4.8 timing chart for i/o interface mode
158 toshiba corporation TMP96C141AF 4.9 timing chart for bus request (busrq )/bus acknowledge (busak ) note 1: the bus will be released after the w ait request is inactive, when the busrq is set to ??during ?ait?cycle. note 2: this line only shows the output buffer is off-states. they dont indicate the signal levels are ?ed. after the bus is released, the signal level is kept dynamically before the bus is released by the external capacitance. therefore, to ? the signal level by an external resistance under the bus is releasing, the design must be carefully because of the level-? will be delayed. the internal programmable pull-up/pull-down resistance is switched active by the internal signal. symbol parameter variable 16mhz 20mhz unit min max min max min max t brc busrq setup time for clk 120 120 120 ns t cbal clk busak falling edge 1.5x + 120 214 195 ns t cbah clk busak rising edge 0.5x + 40 71 65 ns t aba output buffer is off to busak 0 80 080080ns t baa busak output buffer is on. 0 80 0 80 0 80 ns
toshiba corporation 159 TMP96C141AF 4.10 interrupt operation v cc = 5v, ta = -25 c, unless otherwise noted
160 toshiba corporation TMP96C141AF 5. table of special function registers (sfrs) (sfr; special function register) the special function registers (sfrs) include the i/o ports and peripheral control registers allocated to the 128-byte addresses from 000000h to 00007fh. (1) i/o port (2) i/o port control (3) timer control (4) pattern generator control (5) watch dog timer control (6) serial channel control (7) a/d converter control (8) interrupt control (9) chip select/wait control con?uration of the table
toshiba corporation 161 TMP96C141AF table 5 i/o register address map address name address name address name address name 000000h p0 20h trun 40h treg6l 60h adreg0l 1h p1 21h 41h treg6h 61h adreg0h 2h p0cr 22h treg0 42h treg7l 62h adreg1l 3h 23h treg1 43h treg7h 63h adreg1h 4h p1cr 24h tmod 44h cap3l 64h adreg2l 5h p1fc 25h tffcr 45h cap3h 65h adreg2h 6h p2 26h treg2 46h cap4l 66h adreg3l 7h p3 27h treg3 47h cap4h 67h adreg3h 8h p2cr 28h p0mod 48h t5mod 68h b0cs 9h p2fc 29h p1mod 49h t5ffcr 69h b1cs ah p3cr 2ah pffcr 4ah 6ah b2cs bh p3fc 2bh 4bh 6bh ch p4 2ch 4ch pg0reg 6ch dh p5 2dh 4dh pg1reg 6dh eh p4cr 2eh 4eh pg01cr 6eh fh 2fh 4fh 6fh 10h p4fc 30h treg4l 50h sc0buf 70h inte0ad 11h 31h treg4h 51h sc0cr 71h inte45 12h p6 32h treg5l 52h sc0mod 72h inte67 13h p7 33h treg5h 53h br0cr 73h intet10 14h p6cr 34h cap1l 54h sc1buf 74h intepw10 15h p7cr 35h cap1h 55h sc1cr 75h intet54 16h p6fc 36h cap2l 56h sc1mod 76h intet76 17h p7fc 37h cap2h 57h br1cr 77h intes0 18h p8 38h t4mod 58h ode 78h intes1 19h p9 39h tff4cr 59h 79h 1ah p8cr 3ah t45cr 5ah 7ah 1bh p9cr 3bh 5bh 7bh iimc 1ch p8fc 3ch 5ch wdmod 7ch dma0v 1dh p9fc 3dh 5dh wdcr 7dh dma1v 1eh 3eh 5eh admod 7eh dma2v 1fh 3fh 5fh 7fh dma3v
162 toshiba corporation TMP96C141AF (1) i/o port note: when p30 pin is de?ed as rd signal output mode (p30f = 1), clearing the output latch register p30 to ??outputs the rd strobe from p30 pin for psram, even when the internal address is accessed. if the output latch register p30 remains ?? the rd strobe is output only when the external address is accessed. read/write r/w ; either read or write is possible r ; only read is possible w ; only write is possible prohibit rwm ; prohibit read modify write. (prohibit res/set/tset/chg/stcf/andcf/orcf/xorcf instruction) symbol name address 76543210 p0 port0 00h p07 p06 p05 p04 p03 p02 p01 p00 r/w input mode unde?ed p1 port1 01h p17 p16 p15 p14 p13 p12 p11 p10 r/w input mode 00000000 p2 port2 06h p27 p26 p25 p24 p23 p22 p21 p20 r/w input mode 00000000 p3 port3 07h p37 p36 p35 p34 p33 p32 p31 p30 r/w input mode output mode 11111111 p4 port4 0ch p42 p41 p40 r/w input mode 011 p5 port5 0dh p53 p52 p51 p50 r input mode p6 port6 12h p67 p66 p65 p64 p63 p62 p61 p60 r/w input mode 11111111 p7 port7 13h p73 p72 p71 p70 r/w input mode 1111 p8 port8 18h p87 p86 p85 p84 p83 p82 p81 p80 r/w input mode 11111111 p9 port9 19h p95 p94 p93 p92 p91 p90 r/w input mode 111111
toshiba corporation 163 TMP96C141AF (2) i/o port control (1/2) note: with the tmp96c141a/tmp96c141a/tmp96c041a, which requires an external rom, port0 functions as ad0 to ad7; port1, ad8 to ad15; p30, the rd signal; p31, the wr signal, regardless of the values set in p0cr, p1cr, p1fc, p30f and p31f. symbol name address 76543210 p0cr port0 control 02h (prohibit rmw) p07c p06c p05c p04c p03c p02c p01c p00c w 00000000 0 : in 1 : out (when external access, set as ad7 - 0 and cleared to ?".) p1cr port1 control 04h (prohibit rmw) p17c p16c p15c p14c p13c p12c p11c p10c w 00000000 < p1fc port1 function 05h (prohibit rmw) p27f p26f p25f p24f p23f p22f p21f p20f w 00000000 p1fc/ p1cr = 00 : in, 01 : out, 10 : ad15 - 8, 11 : a23 - 16 p2cr port2 control 08h (prohibit rmw) p27c p26c p25c p24c p23c p22c p21c p20c w 00000000 < p2fc port2 function 09h (prohibit rmw) p27f p26f p25f p24f p23f p22f p21f p20f w 00000000 p2fc/ p2cr = 00 : in, 01 : out, 10 : a7 - 0, 11 : a23 - 16 p3cr port3 control 0ah (prohibit rmw) p37c p36c p35c p34c p33c p32c w 000000 0 : in 1 : out p3fc port3 function 0bh (prohibit rmw) p37f p36f p35f p34f p32f p31f p30f w 0000 000 o : port 1 : ras o : port 1 : r/w o : port 1 : busak o : port 1 : busrq o : port 1 : hwr o : port 1 : wr o : port 1 : rd p4cr port4 control 0eh (prohibit rmw) p42c p41c p40c w 000 0 : in 1 : out p4fc port4 function 10h (prohibit rmw) p42f p41f p40f w 000 0 : port 1 : cs /cas
164 toshiba corporation TMP96C141AF i/o port control (2/2) symbol name address 76543210 p6cr port6 control 14h (prohibit rmw) p67c p66c p65c p64c p63c p62c p61c p60c w 00000000 0 : in 1 : out p7cr port7 control 15h (prohibit rmw) p73c p72c p71c p70c w 0000 0 : in 1 : out p6fc port6 function 16h (prohibit rmw) p67f p66f p65f p64f p63f p62f p61f p60f w 00000000 0 : port 1 : pg1 - out 0 : port 1 : pgo - out p7fc port7 function 17h (prohibit rmw) p73f p72f p71f w 000 0 : port 1 : to3 0 :port 1 : to2 0 : port 1 : to1 p8cr port8 control 1ah (prohibit rmw) p87c p86c p85c p84c p83c p82c p81c p80c w 00000000 0 : in 1 : out p9cr port9 control 1bh (prohibit rmw) p95c p94c p93c p92c p91c p90c w 000000 0:in 1:out p8fc port8 function 1ch (prohibit rmw) p86f p83f p82f www 000 0 : port 1 : to6 0 : port 1 : to5 0 : port 1 : to4 p9fc port9 function 1dh (prohibit rmw) p95f p93f p92f p90f wwww 0000 0 : port 1 : sclk1 0 : port 1 : txd1 0 : port 1 : sclk0 0 : port 1 : txd0
toshiba corporation 165 TMP96C141AF (3) timer control (1/4) symbol name address 76543210 trun timer control 20h prrun t5run t4run p1run p0run t1run t0run r/w r/w 0 000000 prescaler and timer run/stop control 0 : stop and clear 1 : run (count up) treg0 8bit timer register 0 22h (prohibit rmw) w unde?ed treg1 8bit timer register 1 23h (prohibit rmw) w unde?ed tmod 8bit timer source clk and mode 24h (prohibit rmw) t10m1 t10m0 pwmm1 pwmm0 t1clk1 t1clk0 t0clk1 t0clk0 w 00000000 00 : 8-bit timer 01 : 16-bit timer 10 : 8-bit ppg 11 : 8-bit pwm 00 : 01 : 2 6 - 1 pwm 10 : 2 7 - 1 11 : 2 8 - 1 00 : to0trg 01 : f t1 10 : f t16 11 : f t256 00 : ti0 input 01 : f t1 10 : f t4 11: f t16 tffcr 8bit timer flip-?p control 25h dben tff1c1 tff1c0 tff1ie tff1is r/w w r/w 00000 1 : double buffer enable 00 : invert tff1 01 : set tff1 10 : clear tff1 11 : don? care 1 : tff1 invert enable 0 : inverted by timer 0 treg2 pwm timer register 2 26h (r)/w (can read double buffer values.) unde?ed treg3 pwm timer register 3 27h (r)/w (can read double buffer values.) unde?ed p0mod pwm0 mode 28h (prohibit rmw) ff2rd db2en pwm0int pwm0m t2clk1 t2clk0 pwm0s1 pwm0s0 rw 0000000 tff2 output value 1 : double buffer enable 0 : over?w interrupt 1: compare/ match interrupt 0 : pwm mode 1 : timer mode 00 : f p1(fc/4) 01 : f p4(fc/16) 10 : f p16(fc/64) 11 : don? care 00 : 2 6 - 1 01 : 2 7 - 1 10 : 2 8 - 1 11 : don? care p1mod pwm1 mode 29h (prohibit rmw) ff3rd db3en pwm1int pwm1m t3clk1 t3clk0 pwm1s1 pwm1s0 rw 0000000 tff3 output value 1 : double buffer enable 0 : over?w interrupt 1 : compare/ match interrupt 0 : pwm mode 1 : timer mode 00 : f p1(fc/4) 01 : f p4(fc/16) 10 : f p16(fc/64) 11 : don? care 00 : 2 6 - 1 01 : 2 7 - 1 10:2 8 - 1 11:don? care
166 toshiba corporation TMP96C141AF timer control (2/4) symbol name address 76543210 pffcr pwm flip-?p control 2ah ff3c1 ff3c0 ff3trg1 ff3trg0 ff2c1 ff2c0 ff2trg1 ff2trg0 w r/w w r/w 00000000 00 : don? care 01 : set tff3 10 : clear tff3 11 : don? care 00 : prohibit tff3 inverted 01 : invert if matched 10 : set if matched; clear if over?wed 11 : clear if matched; set if over?wed 00 : don? care 01 : set tff2 10 : clear tff2 11 : don? care 00 : prohibit tff2 inverted 01 : invert if matched 10 : set if matched; clear if over?wed 11 : clear if matched; set if over?wed treg4l 16-bit timer register 4l 30h (prohibit rmw) w unde?ed treg4h 16-bit timer register 4h 31h (prohibit rmw) w unde?ed treg5l 16-bit timer register 5l 32h (prohibit rmw) w unde?ed treg5h 16-bit timer register 5h 33h (prohibit rmw) w unde?ed cap1l capture register 1l 34h r unde?ed cap1h capture register 1h 35h r unde?ed cap2l capture register 2l 36h r unde?ed cap2h capture register 2h 37h r unde?ed t4mod 16-bit timer 4 source clk and mode 38h cap2t5 eq5t5 cap1in cap12m1 cap12m0 cle t4clk1 t4clk0 r/w w r/w 00000000 tff5 inv trg o: trg disable 1: trg enable 0 : soft- capture 1 : don? care capture timing 00 : disable 01 : t14 t15 10 : t14 t14 11 : tff1 tff1 1 : uc4 clear enable source clock 00 : ti4 01 : f t1 10 : f t4 11 : f t16
toshiba corporation 167 TMP96C141AF timer control (3/4) symbol name address 7654 3 210 t4ffcr 16bit timer 4 flip-?p control 39h tff5c1 tff5c0 cap2t4 cap1t4 eq5t4 eq4t4 tff4c1 tff4c0 w r/w w 0000 0 000 00 : invert tff5 01 : set tff5 10 : clear tff5 11 : don? care tff4 invert trigger 0 : trigger disable 1 : trigger enable source clock 00 : invert tff4 01 : set tff4 10 : clear tff4 11 : don? care t45cr t4, t5 control 3ah pg1t pg0t db6en db4en r/w r/w 00000 fix at ? pg1 shift trigger 0 : timer 0, 1 1 : timer 5 pg0 shift trigger o : timer 0, 1 1 : timer 4 1 : double buffer enable treg6l 16bit timer register 6l 40h (prohibit rmw) w unde?ed treg6h 16bit timer register 6h 41h (prohibit rmw) w unde?ed treg7l 16bit timer register 7l 42h (prohibit rmw) w unde?ed treg7h 16bit timer register 7h 43h (prohibit rmw) w unde?ed cap3l capture register 3l 44h r unde?ed cap3h capture register 3h 45h r unde?ed cap4l capture register 4l 46h r unde?ed cap4h capture register 4h 47h r unde?ed t5mod 16bit timer 5 source clk and mode 48h cap3in cap34m1 cap34m0 cle t5clk1 t5clk0 r/w w 0000 0 000 0 : soft- capture 1 : don? care capture timing 00 : disable 01 : t16 - t17 - 10 : t16 - t16 11 : tff1 - tff1 1 : uc5 clear enable source clock 00 : invert tff6 01 : set tff6 10 : clear tff6 11 : don? care
168 toshiba corporation TMP96C141AF (4) pattern generator (5) watch dog timer t5ffcr 16bit timer 5 flip-?p control 49h cap4t6 cap3t6 eq7t6 eq6t6 tff6c1 tff6c0 r/w w 00 0 000 tff6 invert trigger 0 : trigger disable 1 : trigger enable 00 : invert tff6 01 : set tff6 10 : clear tff6 11 : don? care symbol name address 76543210 pg0reg pgo register 4ch (prohibit rmw) pg03 pg02 pg01 pg00 sa03 sa02 sa01 sa00 w r/w 0000 unde?ed pg1reg pg1 register 4dh (prohibit rmw) pg13 pg12 pg11 pg10 sa13 sa12 sa11 sa10 w r/w 0000 unde?ed pg01cr pg0, 1 control 4eh (prohibit rmw) pat1 ccw1 pg1m pg1te pat0 ccw0 pg0m pg0te r/w 00000000 0 : 8bit write 1 : 4bit write 0 : normal rotation 1 : reverse rotation 0 : 4bit step 1 : 8bit step pg1 trigger input enable 1 : enable 0 : 8bit write 1 : 4bit write 0 : normal rotation 1 : reverse rotation 0 : 4bit step 1 : 8bit step pg0 trigger input enable 1 : enable symbol name address 76543210 wd- mod watch dog timer mode 5ch wdte wdtp1 wdtp0 warm haltm1 haltm0 rescr drve r/w 10000000 1 : wdt enable 00 : 2 16 /fc 01 : 2 18 /fc 10 : 2 20 /fc 11 : 2 22 /fc warming up time 0 : 2 14 /fc 1 : 2 16 /fc standby mode 00 : run mode 01 : stop mode 10 : idle mode 11 : don? care 1 : connect internally wdt out pin to reset pin 1 : drive the pin in stop mode wdcr watch dog timer control register 5dh w b1h : wdt disable code 4eh : wdt clear code symbol name address 7654 3 210 timer control (4/4)
toshiba corporation 169 TMP96C141AF (6) serial channel (1/2) symbol name address 76543210 sc0buf serial channel 0 buffer 50h rb7 tb7 rb6 tb6 rb5 tb5 rb4 tb4 rb3 tb3 rb2 tb2 rb1 tb1 rb0 tb0 r (receiving)/w (transmission) unde?ed sc0cr serial channel 0 control 51h rb8 even pe oerr perr ferr r r/w r (cleared to 0 by reading) r/w 00000000 receiving data bit 8 parity 0 : odd 1 : even 1 : parity enable 1 : error 1: input sclk0 pin (note) overrun parity framing sc0- mod serial channel 0 mode 52h tb8 ctse rxe wu sm1 sm0 sc1 sc0 r/w 00000000 transmission data bit 8 1 : cts enable 1 : receive enable 1 : wake up enable 00 : unused 01 : uart 7bit 10 : uart 8bit 11 : uart 9bit 00 : to0 trigger 01 : baud rate generator 10 : internal clock f 1 11 : don? care br0cr baud rate control 53h br0ck1 br0ck0 br053 br052 br051 br050 r/w r/w 0 000000 fix at ? 00 : f t0 (fc/4) 01 : f t2 (fc/16) 10 : f t8 (fc/64) 11 : f t32 (fc/256) set frequency divisor 0 ~ f (??prohibited) sc1buf serial channel 1 buffer 54h rb7 tb7 rb6 tb6 rb5 tb5 rb4 tb4 rb3 tb3 rb2 tb2 rb1 tb1 rb0 tb0 r (receiving)/w (transmission) unde?ed sc1cr serial channel 1 control 55h rb8 even pe oerr perr ferr sclks ioc r r/w r (cleared to 0 by reading) r/w 0000000 receiving data bit 8 parity 0 : odd 1 : even 1 : parity enable 1 : error 1 : input sclk1 pin overrun parity framing sc1- mod serial channel 1 mode 56h tb8 rxe wu sm1 sm0 sc1 sc0 r/w 00000000 transmission data bit 8 fix at ? 1 : receive enable 1 : wake up enable 00 : i/o interface 01 : uart 7bit 10 : uart 8-bit 11 : uart 9bit 00 : to0 trigger 01 : baud rate generator 10 : internal clock f 1 11 : don? care
170 toshiba corporation TMP96C141AF (7) a/d converter control *1: data to be stored in a/d conversion result reg low are the lower 2 bits of the conversion result. the contents of the lower 6 bits of this register are always read as ?? br1cr baud rate control 57h br1ck1 br1ck0 br153 br152 br151 br150 r/w r/w 0 000000 fix at ? 00 : f t0 (fc/4) 01 : f t2 (fc/16) 10 : f t8 (fc/64) 11 : f t32 (fc/256) set frequency divisor 0 ~ f (??prohibited) ode special open drain enable 58h ode1 ode0 r/w 00 1 : p93 open-drain 1 : p90 open-drain symbol name address 76543210 ad- mod a/d converter mode reg 5eh eocf adbf repet scan adcs ads adch1 adch0 r r/w 00000000 1 : end 1 : busy 1 : repeat mode 1 : scan mode 1 : slow mode 1 : start analog input channel series *1) ad reg0l ad result reg 0 low 60h adr01 adr00 r unde?ed 111111 ad reg0h ad result reg 0 high 61h adr09 adr08 adr07 adr06 adr05 adr04 adr03 adr02 r unde?ed *1) ad reg1l ad result reg 1 low 62h adr11 adr10 r unde?ed 111111 ad reg1h ad result reg 1 high 63h adr19 adr18 adr17 adr16 adr15 adr14 adr13 adr12 r unde?ed *1) ad reg2l ad result reg 2 low 64h adr21 adr20 r unde?ed 111111 ad reg2h ad result reg 2 high 65h adr29 adr28 adr27 adr26 adr25 adr24 adr23 adr22 r unde?ed *1) ad reg3l ad result reg 3 low 66h adr31 adr30 r unde?ed 111111 ad reg3h ad result reg 3 high 67h adr39 adr38 adr37 adr36 adr35 adr34 adr33 adr32 r unde?ed symbol name address 76543210 serial channel (2/2)
toshiba corporation 171 TMP96C141AF (8) interrupt control (1/2)
172 toshiba corporation TMP96C141AF interrupt control (2/2) symbol name address 76543210 dma0v dma 0 request vector 7ch (prohibit rmw) m dma0 start vector dma0v8 dma0v7 dma0v6 dam0v5 dma0v4 w 00000 dma1v dma 1 request vector 7dh (prohibit rmw) m dma1 start vector dma01v8 dma1v7 dma1v6 dam1v5 dma1v4 w 00000 dma2v dma 2 request vector 7eh (prohibit rmw) m dma2 start vector dma2v8 dma2v7 dma2v6 dam2v5 dma2v4 w 00000 dma3v dma 3 request vector 7fh (prohibit rmw) m dma3 start vector dma3v8 dma3v7 dma3v6 dam3v5 dma3v4 w 00000 iimc interrupt input mode control 7bh (prohibit rmw) i0ie i0le nmiree www 000 1 : int0 input enable 0 : into edge mode 1 : into level mode 1 : operate even at nmi rise edge
toshiba corporation 173 TMP96C141AF (9) chip select/wait controller note 1: after reset, only ?lock 2?is set to enable. ? after reset, the program starts in 16-bit data bus, 2-wait state. note 2: these registers can be accessed only in system mode. note 3: tmp96c141a for internal ram less is 80h ~ 7fffh. symbol name address 76543210 b0cs block 0 cs/wait control register 68h (prohibit rmw) b0e b0sys b0cas b0bus b0w1 b0w0 b0c1 b0c0 wwwwwwww 00000000 1 : cs enable 1 : system only 0 : cs0 1 : cas0 0 : 16bit bus 1 : 8bit bus 00 : 2wait 01 : 1wait 10 : 1wait + n 11 : 0wait 00 : 7f00h ~ 7fffh 01 : 400000h ~ 10 : 800000h ~ 11 : c00000h ~ b1cs block 1 cs/wait control register 69h (prohibit rmw) b1e b1sys b1cas b1bus b1w1 b1w0 b1c1 b1c0 wwwwwwww 00000000 1 : cs enable 1 : system only 0 : cs1 1 : cas1 0 : 16bit bus 1 : 8bit bus 00 : 2wait 01 : 1wait 10 : 1wait + n 11 : 0wait 00 : 480h ~ 7fffh 01 : 400000h ~ 10 : 800000h ~ 11 : c00000h ~ b2cs block 2 cs/wait control register 6ah (prohibit rmw) b2e b2sys b2cas b2bus b2w1 b2w0 b2c1 b2c0 wwwwwwww 00000000 1 : cs enable 1 : system only 0 : cs2 1 : cas2 0 : 16bit bus 1 : 8bit bus 00 : 2wait 01 : 1wait 10 : 1wait + n 11 : 0wait 00 : 8000h ~ 01 : 400000h ~ 10 : 800000h ~ 11 : c00000h ~
174 toshiba corporation TMP96C141AF 6. port section equivalent circuit diagram reading the circuit diagram basically, the gate singles written are the same as those used for the standard cmos logic ic [74hcxx] series. the dedicated signal is described below. stop: this signal becomes active ??when the hold mode setting register is set to the stop mode and the cpu executes the halt instruction. when the drive enable bit [drive] is set to ?? however, stp remains at ?? the input protection resistor ranges from several tens of ohms to several hundreds of ohms. po (ad0 ~ ad7), p1 (ad8 ~ 15, a8 ~ 15), p2 (a2 - 23, a0 ~7) p30 (rd ), p31 (wr ) p32 ~ 37, p40 ~ 41, p6, p7, p80 ~ 86, p91 ~ 92, p94 ~ 95
toshiba corporation 175 TMP96C141AF p42 (cs2 , cas2 ) p5 (an0 ~ 3) p87 (int0) p90 (txd0), p93 (txd1)
176 toshiba corporation TMP96C141AF nmi wdtout clk ?a , am8/16 ale reset
toshiba corporation 177 TMP96C141AF x1, x2 vref, agnd
178 toshiba corporation TMP96C141AF 7. guidelines and restrictions (1) special expression explanation of a built-in i/o register: register symbol ex) trun . . . bit t0run of register trun read, modify and write instruction an instruction which cpu executes following by one instruction. 1. cpu reads data of the memory. 2. cpu modites the data. 3. cpu writes the data to the same memory. ex1) set 3, (trun) . . . set bit3 of trun ex2) inc1, (100h) increment the data of 100h the representative read, modify and write instruction in the tlcs-900 set imm, mem, res imm, mem chg imm, mem, tset imm, mem inc imm, mem, dec imm, mem rld a, mem, add imm, reg a 1 state one cycle clock divided by 2 oscillation frequency is called 1 state ex) the case of oscillation frequency is 20mhz. (2) guidelines e a , pin fix these pins vcc or gnd unless changing voltage. warming-up counter the warming-up counter operates when the stop mode. is released even the system which is used an external oscillator. as a result, it takes warming up time from inputting the releasing request to outputting the system clock. a high speed m dma (dram) refresh mode) when the bus is released (busak = 0) for waiting to accept the interrupt, dram refresh is not performed because of the high speed m dma is generated by an interrupt. programmable pull up/down resistance the programmable pull up/down resistors can be selected on/off by program when they are used as the input ports. the case of they are used as the out- put ports, they cannot be selected on/off by pro- gram. ? bus releasing function refer to the note about the bus release in 3.5 func- tions of ports because the pin state when the bus is released is written. ? watch dog timer when the bus is released, both internal memory and internal i/o cannot be accessed. but internal i/o cantinues to operate. so, the watch dog timer contin- ues to run. therefore, be carefull about the bus releas- ing time and set the detection timer of watch dog timer. 2 watch dog timer the watch dog timer starts operation immediately after the reset is released. when the watch dog timer is not used, set watch dog timer to disable. 3 cpu (high speed m dma) only the ldc cr, r, ldc r, cr instruction can be used to access the control register like transfer source address register (dmasn) in the cpu.

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